# π¬ The Harvester: ultimate power supply for the Raybeacon DK

• What method or methods are you using to characterize your solar cells? I'm guessing in this instance that for the different illumination levels you are recording the open circuit voltage and the short circuit voltage?

@NeverDie exactly. That was a quick and dirty measurement using a multimeter. The P (Β΅W) value was calculated as V * I * 0.8 (MPP assumed 80%, I must multiply to 0.8^2 instead). My intent was to describe the panels in dependency of different illuminance (which must be also denoted by E instead).

Finding MPP on IV curve is the right method to characterize a cell. But that would require fixing illuminance at some point (and is more complicated), when I was more interested in different light conditions. Most cells are rated at 200 lux indoors, and one sun (more than 100k lux) outdoors. Perhaps 50 lux indoors (a typical light at home) and 1000 lux (cloudy day) is more practical for low-light purposes so I could trace IV curves for the cells I ordered at that illuminance levels.

Looks as though you can get a fairly inexpensive digital light sensor from adafruit that will tell you the lux level

It seems my phone uses Sensortek STK3310 or similar. At low light might be as accurate as those two, but is limited at higher levels indeed. Would be nice to replace it with more reliable solution, will try to find out a luxmeter in a local fablab or get one of those you've suggested, thanks!

• I built the op-amp circuit, and now the open circuit readings on a solar cell are much higher than when I was taking the readings with a regular multimeter. As long as I can keep the control logic current at just a couple hundred nanoamps or so, I think I'll probably have enough voltage under even very dim lighting that I doubt cold start will be an issue.

There is the Ricoh R1800K which consumes just 144nA and can start from a 0.72 Β΅W source. It requires at least 2V to operate, but schematic is very miniature - only three more components needed.

• R1800K

Interesting chip. On the one hand, it seems aimed at small solar cells because of the low quiescent current and because it can't handle more than 1 or 2ma tops. On the other hand, it doesn't have MPPT but instead wants you to pick a single MPP voltage (out of the choices that RICOH provides) that it should operate at. Not sure how good being tied down like that would be in actual practice. Maybe it would be fine in an office environment where you could perhaps assume steady, uniform lighting...?

• I switched to a deadbug build using an MCP6S22 opamp for a buffer because I was getting too much conductance/noise on a pCB with the other op amp. Everything has to be soldered together, because otherwise current gets lost through the connectors when dealing with such miniscule currents.

Having done that, for the keychain solar cell I measured open circuit voltage at 2.66v at 1 lux (according to my lux meter that I mentioned above, so take that measurement for whatever it's worth) and a short-circuit current of 88na, according to a uCurrent Gold (but with the voltage measuring opamp circuit still soldered into place).

This has me wondering now how much of a voltage (non-boosted) it could eventually generate onto a capacitor, so I suppose that's the next thing to try. I'll try it first with my simple solar charger: https://www.openhardware.io/view/620/Supercap-solar-charger
since that's easy, but for a more accurate measurement I may need to construct a deadbug equivalent using just a diode and capacitor. That would be a lower bound for the dead simple approach which then perhaps some harvester could improve upon, though I'm not sure any of the commercial energy harvesters are spec'd at that low of a power.

This also explains why measuring the voltage of the solar cell with just a volt meter (with no op amp circuit to help it) is hopeless at such low light levels: 2.66v divided by 10MOhm is 266 nanoamps, where 10MOhm is the typical digital volt meter input resistance. i.e. the 266 nanoamps drain through the volt meter would be approximately 3x the amount of current that the solar cell can generate, thereby causing a large error in the voltage measured by the DMM.

Edit2: I connected a 100uF ceramic capacitor in parallel with the solar cell (I didn't bother with adding a diode), and it charged up to 2.778v. Somehow that's slightly higher than the previously measured open circuit voltage of 2.66v. Not sure how that is, but perhaps the orientation of the solar cell was a little more favorable when this measurement was taken. In any case, I think whatever the open circuit voltage is, you can probably charge up to that amount with any size low leakage capacitor that you want to use. So, from this point of view, choosing a solar cell which generates high open circuit voltages in very dim light is perhaps more important than any other decision if what you want is something that can get past startup even if the available power is only minuscule.

The only thing needed is a simple control circuit which, if possible, consumes little or no energy until it reaches the desired voltage range, whereupon a more sophisticated control circuit can take over. Something like a schmitt trigger might work, but it would need to draw extremely little current, which not all schmitt triggers do, especially as they approach the threshold voltage. Any ideas?

Perhaps something like: https://hackaday.com/2018/07/19/energy-harvesting-design-doesnt-need-sleep/
or perhaps a solar engine control circuit might work: http://beambuilder.blogspot.com/p/solar-engines.html
or...???
Since they all do more or less the same thing (charging a capacitor to a threshhold voltage and then "turning on"), the challenge would be to find (or invent) a circuit which achieves that result but while consuming the absolute least amount of power that current technology allows. A lot of the published designs use older technology, and so I suspect better possibilities exist if leveraging newer, more capable components.

• @NeverDie Wow, I'm really surprised with so high voltage of the panel. Thank you for sharing the measurements!

My understanding is that OC voltage is defined by amount of free electrons in the depletion zone, and hence by the width of the zone. When in the light, more electrons will fill the zone, but there seem to be some saturation threshold limiting the max voltage. It would be interesting to somehow measure the electric field in the full absence of light. Also, capability to emit new electrons in the depletion zone defines the max current from the cell. It looks like crystalline cells can do it more effectively than amorphous, but the latter have wider depletion zone in the dark.

I don't know how to use so ultra-low current sources. The harvester should be able to work from 100 nanoamps or below. This limits design to a linear charger only (at least at frontend) - anything more complex (like a boost or buck circuit) would require higher quiescent current which will collapse the cell.

A MOSFET may draw as low as few nanoamps so virtually it could be possible. The PV cell needs to be isolated from the load to prevent voltage drop on the FET which may cause it defunct. Perhaps an isolated capacitor will be required to sustain the FET state while input capacitor releases its charge. The FETs may require resistors to shift voltage level, but again, they need to be hundreds of megohm. This will also impact switching speed. Perhaps some sort of hiccup switching circuit may make it. Also, I see some similarities with how dynamic RAM implemented.

For a usual solution, there are some ideal diode like the MAX40203 with 300 nA quiescent current. I suspect that the charge pump of the SM74611 may draw microamps when in ON state - it's unclear from the datasheet.

All in all, it looks like a puzzle

• If you're able to run in some kind of duty cycled mode, where the control circuitry is only active for brief periods of time, then perhaps the quiescent currents get averaged down to a more manageable level. As a first step, I think I'll just blithely assume the control circuitry can access at least some conventional voltage levels (either saved up from earlier energy harvesting or else gathered in a crude way like in my example above). If I can make good progress doing that, then I can always revisit that assumption at a future date.

• Found a nice paper on charge pumps design: https://www.mdpi.com/2079-9292/8/5/480.

• TPL5100, which draws just 30na, looks promising for duty cycling the control circuitry:
http://www.ti.com/lit/ds/symlink/tpl5100.pdf
It has both a PGOOD pin as well as a mosfet driver pin. The edge case would need confirming that it can slowly power up from zero volts to its minimum 1.8v operating voltage with only just over 30na source current without itself drawing more than 30na. Since it has a PGOOD pin, I'd wager that it's unlikely to emit false positive signals while still charging at below 1.8v, because if it did the PGOOD pin would be worthless.

• Found a nice paper on charge pumps design: https://www.mdpi.com/2079-9292/8/5/480.

@Mishka I read a similar paper (http://citeseerx.ist.psu.edu/viewdoc/download;jsessionid=D650012CC6F5208E02BF41AE55DF0E95?doi=10.1.1.128.4085&rep=rep1&type=pdf) which says that the best charge pumps use static charge transfer switches. That said, I'd be happy if I could build any kind of ultra low energy harvesting charge pump using discrete components as long as the component count is low.

• I tried it with a TPL5110 just now, but it gets caught in a boot loop: voltage rises to 1.440v and then suddenly drops to about 1.400v. I think this is because when the TPL5110 starts up for the first time, it draws ~200ua current to read the resistor settings, which it then stores and uses for the time delay.
So, if there exists a similarly low current timer that can be set without a heavy drain step like that just described, then I'd go for that instead.

Meanwhile, this is the lowest current (88na) voltage detector that I know of: https://www.torex-usa.com/products/voltage-supervisors/low-power/xc6136/
That would limit me to light sources something greater than 1 lux (as measured by my lux meter) if I am to harvest anything using the brute force simple approach for a cold start, but once I get enough of a power reserve I could maybe harvest lesser amounts by duty cycling something like an LTC3108.

• @NeverDie Maybe try to bootstrap it with external voltage source applied parallel to the cell?

• @NeverDie Maybe try to bootstrap it with external voltage source applied parallel to the cell?

I'm not sure what that would look like. Do you have anything concrete in mind?

• @NeverDie So when TPL5110 has passed the boot phase does it work after that?

• @NeverDie So when TPL5110 has passed the boot phase does it work after that?

Ah, good question. Then it seems to work just fine. I had it waking once every 10 seconds and weakly flashing an amber LED, all on just 88na of collected solar current. Essentially, the capacitor voltage would drop to just below the forward voltage of the LED during the flash (effectively self terminating the flash duration) and then it would charge back up from there.

• @NeverDie Oh, nice! It's interesting that the full circle including oscillator consumes so low power. It seems really possible to build a discrete harvesting circuit which can collect enough charge to execute a single duty cycle of an MCU.

Such, assuming (88-35) nA/s = 53 nC charge it will require less than 5 minutes and 22 Β΅F capacitor in order to shot a single BLE event from an nRF52 MCU. And that's at so ridiculous low light. Quite awesome, I think.

The only issue is that the timer can't optimize it for faster charge, but a voltage driven latch could.

• @Mishka Just FYI, in my experiment I drove the LED directly from the DRV pin (I didn't use a MOSFET), and I didn't bother with setting the DONE pin, since I wasn't using a MCU. That gave a maximum possible flash duration of 50ms once every 10 seconds, but like I said, it self-terminated before the full 50ms was up because the capacitor voltage dropped below the forward voltage of the LED. Using a mosfet and an MCU, as intended, would give a little more control, since the the MCU could issue a DONE signal.

So, yeah, it really is impressive what can be done with so little light, and it could actually go with even less light and a longer charge time, provided the startup hurdle can be gotten past.

Unfortunately, the XC6136 doesn't yet seem to be widely available at the the all the different possible voltages that can be detected. Digikey doesn't have any, and mouser has only just 3 different types. Perhaps that will improve in the future.

So, perhaps this is a case where powering the TPL5110 from a primary cell would be an acceptable "cheat". At just 35na, that primary cell should last a very long time.

• I received a 0.02% accurate 500,000 count DMM that should make measuring changes by small voltage and current amounts a bit easier:

http://youtu.be/M3xDX1Jq55M

If you're in the market for such a thing, now is a good time to buy, as prices are lower than I have ever seen before and a number of the models previously available from Extech, Brymen, GreenLee, AmProbe and other labels have been discontinued (permanently, it would seem). The models still in production cost 2-3x as much, as did the discontinued models up until fairly recently.

Interestingly, in the dead of night the keychain solar cell can nonetheless pull down 1.3v from a window facing a streetlight that's across the street, as measured with the op amp buffer using a DMM. That amount of light is so low that it registers as 0.2 lux on my lux meter. On the other hand, it also measures 0.2 lux even with the lens cover on, so I think it's below my lux meter's ability to measure it, as the 0.2 lux appears to be just an offset that should be calibrated to zero.

An alternative to the opamp buffer would be to have the solar cell charge a 0.1uF capacitor, which then gets quickly read by an arduino ADC. I haven't wired that up yet, but I expect the results would be about the same.

Or, you could charge a larger capacitor for a longer period of time and perhaps try to snag it with a peak voltage reading when you first connect to it with your DMM. I haven't tried this. I expect it would work, at least to some degree, if you used a big enough capacitor and charged it for long enough, so it might be worthwhile if you have lots of patience.

Interestingly, the typical input resistance for an oscilliscope is only 1 MegaOhm. For a typical DMM, it's 10 MegaOhm, and for an atmega328p ADC, it's 100 MegaOhm. Thus, if measuring 5 volts, the Arduino ADC would experience a 50 nanoOhm drain. That's too high for measuring weakly sourced solar voltages under very dim lighting. 10 gigaohm would be preferable, but then it will take some time to charge up an input capacitor for the ADC to read.

It would be better to leave the input impedance as is but use software to disconnect the input pin when it's not being used. That's certainly possible with an nRF5x, but I'm not aware of that being possible on an Arduino Uno. Is it?

I could connect/disconnect it with a mosfet or a transistor, but then we're back to supplementing the arduino uno with more hardware again, and the voltage drop across such hardware needs to be adjusted for, since the whole point is to get an accurate voltage measurement.

• Interestingly, in the dead of night the keychain solar cell can nonetheless pull down 1.3v from a window facing a streetlight that's across the street, as measured with the op amp buffer using a DMM. That amount of light is so low that it registers as 0.2 lux on my lux meter.

It would be interesting to measure voltage when the panel is dead black. Should be possible by wrapping it into paper and then aluminum foil. In theory it should be perfect zero, but connecting wires and the cell itself may work as antenna and hence the opamp may show some bias.

An alternative to the opamp buffer would be to have the solar cell charge a 0.1uF capacitor, which then gets quickly read by an arduino ADC. I haven't wired that up yet, but I expect the results would be about the same.

Yeah, the charge capacitor is part of some ADC implementations. But instead of use of comparators it might be possible to measure charge / discharge time and derive current and voltage from that. Also, knowing the charge current it will be easy to derive time to full charge and select proper capacitor.

It would be better to leave the input impedance as is but use software to disconnect the input pin when it's not being used. That's certainly possible with an nRF5x, but I'm not aware of that being possible on an Arduino Uno. Is it?

From my understanding, input impedance of most of MCU ADC pins (when disabled) are defined by MOSFETs and hence is subject to implementation and input voltage. But with the charge capacitor large enough it should be not an issue, at least as long as the capacitor wasn't connected to the ADC port during the charge (otherwise the impedance must be gigohms in order to be negligible small). Perhaps a mechanical switch could better solve it for the task. And then MCU can be used to measure time to discharge and do the math.

Also, I must note that to charge the capacitor with tens of nanoamps, the harvester control circuit must consume something in picoamps And this makes me think that, first, there must be a reasonable bottom limit, and, second, a combined RF / solar harvester may be an interesting option to go, especially taking in account they can be connected to the same input.

• It would be interesting to measure voltage when the panel is dead black. Should be possible by wrapping it into paper and then aluminum foil. In theory it should be perfect zero, but connecting wires and the cell itself may work as antenna and hence the opamp may show some bias.

OK, I'll try it and let you know.

Also, I must note that to charge the capacitor with tens of nanoamps, the harvester control circuit must consume something in picoamps

You're right, there just aren't going to be any control circuits that run on mere pico-amps on a continuous basis, and that sets the limit on how low you can go. It's for that very reason that I'm hoping to find some kind of ultra low current, very low frequency, low voltage self starting circuit that effectively draws almost no current until it starts up. It wouldn't have to start at a precise voltage. Just in a general ballplark. Maybe something like this, except lower voltage than 3v?
http://www.discovercircuits.com/DJ-Circuits/3na-osc.htm
Seems like it should be possible, given progress in the components since that circuit was drawn, which is now quite a while ago.

If so, maybe it could even be used to drive a boost converter, similar to:

and with a high enough voltage, perhaps a voltage multiplier as well:

http://dangerousprototypes.com/blog/2013/07/20/avalanche-pulse-generator-and-some-scope-porn/

Basically, the circuit needs to remain inert until enough charge builds up and a trigger gets tripped. And, it needs not to bootlooop even though it ramps up using just very little current. A tall order, I know. Not sure if the right kind of circuit exists, but that's what I'm in the hunt for.

If not a multivibrator, then maybe a ring oscillator. Or, if not that, then a blocking oscillator. And if not that, ...., who knows? There are lots of research papers published where people have been able to do it, but unfortunately a lot of them are IEEE published, and so I don't have access to the details of how it has been done. For sure, a lot of it is instantiated into a CMOS chip, which is beyond my reach anyway, but some of them do seem to use discrete components.

If you have any suggetions, I'm all ears.

• @Mishka said in The Harvester: ultimate power supply for the Raybeacon DK:

It would be interesting to measure voltage when the panel is dead black. Should be possible by wrapping it into paper and then aluminum foil. In theory it should be perfect zero, but connecting wires and the cell itself may work as antenna and hence the opamp may show some bias.

OK, I'll try it and let you know.

@Mishka 8mv was as low as I could take it, but I suspect even then there may have been some slight amount of light getting at it. The room was very dark, but I could make out shapes with night vision, and the backlight on my Fluke 87v was leaking light all over the place, even though I tried to shield it. To really do it properly I'd probably have to set up a wireless link so that I could be in another room to read the voltage. Either that or set up a logger and check it after-the-fact. So, summarizing, I apologize I didn't do a more thorough job, but for being conducted in the middle of a pandemic I did the best that time allows, and besides, 8mv is pretty close to zero, so I hope that answers your question well enough. As a cross-check to rule out the possibility of it being an artifact, I'll sometime soon take the measurement in a brief snapshot using an arduino, without the aid of an op-amp, and see how that compares. I'll probably use a load switch to disconnect the arduino so that the solar cell has a chance to charge up a capacitor between readings, and I anticipate that given enough time it will eventually charge up to the open circuit voltage.

Should I start a separate thread for this, or continue it here? It seems that your project is completed, and although this is all relevant, maybe it would be better to split it off? @Mishka Since you're the OP, what's your preference? Continue as is, or fork your thread and continue in a separate thread? I'm enjoying the collaboration, and hope you feel the same. I'm fine with either choice.

• In case anyone is curious, this is the dead-bug setup I used to do the op-amp assisted measurements:

The op-amp calls for a bypass capacitor to be soldered within one millimeter of the input signal, so I soldered a small surface mount ceramic cap directly to that pin and then ran a wire to it from the GND pin. Not sure how well you can see it, but here's a photo of that:

The LDO had similar capacitor requirements, and I was able to solder those directly between its pins:

Maybe because of that, despite all the long wires, noise didn't seem to be a problem. The reason for the deadbug design and the DIP op-amp was to avoid any leakage currents that might happen if it were all mounted properly to a protoboard, as I've read accounts from others who have tried doing that but who ran into leakage problems.

So, while I admit it looks awfully scruffy, it doesn't matter, because it's purpose built just to help get accurate open circuit voltage measurements (and short-circuit current measurements with a uCurrent Gold, not shown here).

• And here is Version 2, which uses an Arduino UNO to and a load switch to measure an E-PEAS solar module that's charging a 100uF capacitor using a solar keychain solar cell. This time I did use a prototype board.

It's too soon to evaluate, but it seems as though it's off to a good start....

Edit: nope. I'll have to migrate the Arduino design to dead-bug, because the voltage is only very slowly crawling up. Maybe that's just how it is with this the E-PEAS, or else maybe mounting leakage (the higher the voltage the higher the leakage) is what's causing the drag.

Edit2: confirmed. These measurements were taken at 1 minute intervals, under varying cloud conditions, and it's clearly not able to hold on to the charge the E-PEAS has accumulated on the 100uF ceramic cap:

``````734, raw = 652, volts = 3.267
735, raw = 689, volts = 3.453
736, raw = 371, volts = 1.859
737, raw = 399, volts = 1.999
738, raw = 445, volts = 2.230
739, raw = 556, volts = 2.786
740, raw = 616, volts = 3.087
741, raw = 671, volts = 3.362
742, raw = 371, volts = 1.859
743, raw = 444, volts = 2.225
744, raw = 510, volts = 2.556

``````

• I punted on the Arduino and hooked up the E-Peas AEM10941 module to the deadbug op-amp for measurement, as the dead-bug op-amp appears to work flawlessly. The results were: the AEM10941 does build up to a voltage of about 4.135v max when under fairly bright lighting, and then all that disappears and it reverts to starting to charge up again from a voltage of about 1.8v, and it cycles over and over like that. Kinda weird, but that unexpected result may explain the above 1 minute interval readings: probably (?) it wasn't current leakage but instead this kind of cycling that explains the measurements.

Edit: Unfortunately, the AEM10941 breakout board can't seem to rise above 0.352 volts when tested with the same solar cell and same dead-bug op amp assembly under the same 1 flux light source, so I'm afraid I have to label it a FAIL for use in boosting, just by itself, from that particular low light scenario. Given its datasheet, I'm rather disappointed. I did clean the board and my soldered connections pretty thoroughly with IPA, but perhaps there are other leakages inherent in that board, or perhaps the chip itself has limitations that maybe aren't apparent from its datasheet.

Which raises an interesting question: are some types of PCB's less prone than others when it comes to leakage currents? It might make a difference in what kind I order from a PCB fabhouse if some types are better than others. Anyone know?

I didn't test whether the AEM10941 might have some other beneficial use if that barrier is somehow passed, or assisted in being passed, but for now I'm moving on to test some other chips and see how they perform under these conditions to see whether they perform any better and without needing help.

Edit: BQ25504 has no problem charging under the 1 lux light, under the same conditions, even from a starting voltage of zero volts.

Edit2: Well, not quite. Despite a promising start, the BQ25504 peaked at 0.812v and couldn't seem to pull itself above that. It was able to charge up further than the AEM10941, but it hit a ceiling nonetheless. So this time I gave it some bright light to bring its supercap voltage up to 0.814v, and now the voltage appears to be climbing again, al beit slowly. Assuming it is able to continue on its own from this point forward, then my theory is that internally there is a schmitt trigger which is causing this effect: as the voltage slowly rises, the current drain increases up to a peak and then declines again as the voltage continues to rise. At least that is how TI describes typical schmitt trigger behavior in Figure 1 of TI's application report entitled "Understanding Schmitt Triggers": http://www.ti.com/lit/an/scea046/scea046.pdf

Vertical axis is current and horizontal access is voltage.
So, if that peak current drain is greater than the current generated by the solar cell at the 1 lux light level, it simply can't push past it to the other side.

Both chips seem rather pathetic if, as seems to be the case, a solar cell alone and without assistance can charge up a capacitor to its open circuit voltage of somewhere around 2.7v but they can't. To be fair, there could be other factors in play, though, like the PCB material type, the dialectric the manufacturer used to impregnate the FR4 to make the PCB, how much humidity had gotten into the FR4 (resulting in extra leakages), component choices as well as layout. That was my earlier hunch, but that hunch may get upended and replaced with the schmitt trigger theory if the BQ25504 continues its upward charge. We shall soon see.

Meanwhile, somewhere I have laying around a BQ25570 on a chinese breakout board, and it might (?) possibly avoid this problem that the other two seem to share....

Edit3: Nope. The BQ25504 simply got stuck again, this time at 0.851v. According to the datasheet, it's still in cold-start mode until the voltage on VSTOR reaches at least 1.6v (or possibly higher), and that matches what I recall about the BQ25504 from earlier experimentation with it: it performs pretty terribly while in cold-start mode.

Punt!

Unfortunately, BQ25570 also remains in cold start mode up to the same 1.6v+ as the BQ25504, so I'm losing optimism that it might be any better... And like the BQ25504, the BQ25570 also requires typically 15uw to get its mojo on, and at 88na of current that just isn't going to happen.
So, there's no rush to test the BQ25570. If the datasheet is right, it's almost certainly another FAIL. Judging from the datasheet, the BQ25570 is largely just the BQ25504 mashed together with a buck converter. And the BQ25505 looks about the same as the BQ25504, except with a little bit less quiescent current.

What a disappointment! I would have thought that TI had the in-house talent to do a lot better than this.

• Well, doing a little back of the envelope calculations: if a silver zinc 8mah SR416 primary battery, which is just 4.8mm in diameter and 1.6mm thick, were used to continuously drive a 35na TLV5110 timer, then assuming all 8mah could be extracted and ignoring self discharge, it would last for 26 years. Then consider that a properly designed energy harvesting circuit could relieve the battery from needing to run whenever there is adequate harvested energy available, and the expected lifespan of the system would probably be even longer.

The only purpose of the timer would be to pulse accumulated energy into an off-the-shelf energy harvester, probably none of which can handle extreme low energy accumulation. One maybe can't know what the optimal duty cycle should be, but one could make educated guesses, and perhaps a more refined circuit could even self adapt to some degree.

Anyhow, I'd rather not go that route, but as an exploratory tool, it would be fun to make these harvesters work in "scotopic" darkness and yet still accomplish something useful with whatever energy they can somehow squeeze out of it, all while remaining tiny.

• Hi @NeverDie, thanks a lot for doing the experiments!

Basically, the circuit needs to remain inert until enough charge builds up and a trigger gets tripped. And, it needs not to bootlooop even though it ramps up using just very little current. A tall order, I know. Not sure if the right kind of circuit exists, but that's what I'm in the hunt for.

Yeah, this is would be very interesting to achieve indeed. Looks like the water bucket from aquapark. Unfortunately, have no practical ideas at the moment. Maybe a FET + BJT combo where the FET generates spike of the current which activates the BJT which then drains the input capacitor? The idea here is to utilize the inrush current from the FET before it will be stabilized. A comparator may have higher quiescent current, or may not.

8mv was as low as I could take it, but I suspect even then there may have been some slight amount of light getting at it. The room was very dark...

8 mv is fair enough. So it seems all about the structure of the amorphous cell. Interesting!

Should I start a separate thread for this, or continue it here? It seems that your project is completed, and although this is all relevant, maybe it would be better to split it off? @Mishka Since you're the OP, what's your preference? Continue as is, or fork your thread and continue in a separate thread? I'm enjoying the collaboration, and hope you feel the same. I'm fine with either choice.

Although the discussion went beyond the original project, the topic is very interesting. While most of existing harvesters are aimed at low-voltage sources, it seems that we're trying to address the unique property of a-Si cells to have high-voltage bias in the extremely low light. This is not only enjoying, but might also have (and I hope will do) some practical extension. Of course, if there is a better place for the discussion - it's completely okay to move it, I'll be glad to follow-up there.

Regarding the project, it wasn't finished yet. I'm currently waiting for newest PCBs - they're still based on SPV1050, fully configurable, the components selection is for the boost. Appropriate solar panels are also on the way.

BTW, I had a chance to try the SPV1050 (buck) and nRF52833 with a single one SolarBit I have, no battery attached. In the direct sunlight it works without any issue, even with 1 mA red LED blinking 50% of time. This is definitely not the best setup, so the mentioned PCBs and panels should make it more useful and especially for a cloudy day. Also, for the version 2.0 I'm considering to replace the harvester IC with the AEM1094. I also have somewhat different idea about form-factor, but that's for another topic.

And here is Version 2, which uses an Arduino UNO

Perhaps the right thing would be to charge the capacitor first, and only after that connect it to the Arduino. The Arduino has to read the ADC often so it should be possible to determine highest voltage before it decays.

Unfortunately, the AEM10941 breakout board can't seem to rise above 0.352 volts when tested with the same solar cell and same dead-bug op amp assembly under the same 1 flux light source, so I'm afraid I have to label it a FAIL for use in boosting, just by itself, from that particular low light scenario.
...
Despite a promising start, the BQ25504 peaked at 0.812v and couldn't seem to pull itself above that.

From my (perhaps not too careful) review I did earlier in this thread the AEM10941 requires 3 Β΅W input, and the BQ25504 requires 15 Β΅W. Either of those are far beyond the 3V*80nA condition.

Unfortunately, by most of manufacturers a nanoamp source seem usually considered as zero current.

if a silver zinc 8mah SR416 primary battery, which is just 4.8mm in diameter and 1.6mm thick, were used to continuously drive a 35na TLV5110 timer, then assuming all 8mah could be extracted and ignoring self discharge, it would last for 26 years.

Hmm... taking in account those 80 nA collected in 10 seconds will be wasted in one millisecond, and then the next 9.999+10 seconds it will wait for another portion, it sounds like bargaining 35 nA for 40 nA. Well, fair enough!

• Hmm... taking in account those 80 nA collected in 10 seconds will be wasted in one millisecond, and then the next 9.999+10 seconds it will wait for another portion, it sounds like bargaining 35 nA for 40 nA. Well, fair enough!

TI makes a range of different TLP5xxx chips, and Adafruit makes convenient breakout boards for at least two of the different models. I even used one in an earlier leak detection project: https://www.openhardware.io/view/534/Extremely-Simple-Arduino-Pro-Mini-LoRa-Water-Leak-Detector

What I haven't yet tested (and haven't read nor heard) is whether ia TPL5xxx can self excite and start-up normally if powered from the very slowly rising voltage created by a tiny solar cell in weak lighting.

• I stumbled across this: http://www.prc68.com/I/JouleThief.shtml
which is a fascinating goldmine of information about blocking oscillators and their use in just about every cheap solar circuit you've ever seen or heard of, including some that maybe you haven't. Be that as it may, for tiny panels in ultra low light (1 lux and below), I'm pretty sure they'll need to be spoon fed, just like these commercial chips we've been examining.

As for a proper DIY trigger circuit, about 5 years ago David Pilling made some very interesting posts regarding the use of PUTs (programmable unijunction transistors): https://www.davidpilling.com/wiki/index.php/PUT
and on his wiki he built some solar harvesters around that. What I really like and appreciate about his work is that he published ltspice models of his circuits, so it's very easy to download them and run the simulations. Earlier today I emailed David Pilling to see if he'd like to join the discussion here. A lot of technological progress in ultra low power has happened over the last 5 years, and so I think maybe he would be interested and perhaps he'd want to upgrade his circuitry to take advantage of the much lower-voltage/lower-energy components commonly available now that simply didn't exist back then.

Hmm... taking in account those 80 nA collected in 10 seconds will be wasted in one millisecond, and then the next 9.999+10 seconds it will wait for another portion, it sounds like bargaining 35 nA for 40 nA. Well, fair enough!

What I forgot to mention in the post directly above was that the tlp5xxx chips can be resistor programmed for much longer cycles than 10 seonds. e.g. the TLP5110 can be set anywhere from 100ms delay all the way up to a 2 hour delay. So, that's a very pliable range for collecting tiny amounts of solar on a cap, which can then be fed into a harvester as a unified kick. The 10 seconds you're referring to just an arbitrary number that I had picked and which just happened to work in the earlier circuit. The time delay could be set much less or much greater than 10 seconds. It's whatever you choose.

I think I'll try a tpl5xxxx timed collector and then pipe the accumulated current into the LTC3508 circuit through an ultra low leakage load switch. Since the LTC3801 needs only 20mv, it should be easy to collect at least that voltage level, even in very dark conditions, using the solar keychain solar cell (amorphous silicon): https://www.openhardware.io/view/732/Extreme-Energy-Harvester So, while the hunt is on for something better and more elegant as a trigger than the crudity of just how much time has passed, this is a brute force approach whose virtue is that it's pretty much guaranteed to work provided that leakage currents are tightly controlled to extremely low levels Fortunately, because of ohm's law, ultra low voltage is likely to make ultra low leakage easier to achieve during the accumulation phase. What will be interesting is: 1. how big a cap is needed and 2. how long the cycle time needs to be, because boosting extremely low voltages still needs to meet the minimal power requirements (i.e. a lot of current). Unfortunately, nowhere that I can find in the LTC3108 datasheet does it specify the minimum input power to operate. Just the 20mv minimum voltage. Therefore, I'm guessing the minimum power is probably rather high, since companies often hide their bad news by simply not reporting it in the datasheet. Anyhow, I'll just have to derive the minimum power as best I can through experimentation.

The main downside to the TPL5xxx is that it reads the resistor values exactly once during the startup phase, and then never again. Although that has the benefit of limiting forever after the amount of current the TPL5xxx needs to operate, it also means that you can't easily change the periodicity anytime after the TPL5xxx starts up: even if you change the resistors after it gets going, it never reads them again. Thinking ahead, it might (?) be possible to hack around that limitation by changing the resistor values and then power cycling the TPL5xxx so that it reads the new values and incorporates them. The tradeoff for that result though is the extra circuitry needed to accomplish that. It would be much easier if (?) one of the TPL5xxx variants had a reset pin, so perhaps I'll look soon into whether or not any of them have that feature....

• I put David Johnson's 3na oscillator circuit:
http://www.discovercircuits.com/DJ-Circuits/3na-osc.htm
into LTSpice and ran the simulation, and it looks promising:

It also runs just fine at 2v. Fairly easy to get a shorter or longer cycle by tweaking the resistor values and/or capacitor values.

The voltage swing is even better than I was expecting: it drops all the way down to around 30 or 40mv.

Of course, it would be nice if it could run at even lower voltages than 2v. Seems like that should be possible. Anyone have suggestions for which transistors to try for that?

The simulation shows that there's a very nice current pulse of about 4.2ma through Q2 during the very brief discharge phase, so I'm guessing that could drive a buffer transistor to turn on hard, which in turn could, in theory, drive a meaningful load without disturbing the underlying timer circuit. If that's the architecture, though, there may need to be a separate, isolated capacitor to drive the load that charges up in parallel with the capacitors in this oscillator circuit--unless perhaps there's some way to recycle/reuse the current that gets dumped and otherwise wasted during each discharge.

Or, quite possibly, it could be used to drive a flyback type circuit, in which case I possibly wouldn't need a commercial boost chip at all and could instead do all the boosting with a homemade DIY circuit made out of discrete components. That's the promise of what this type of low-level control could grant.

Edit: I posted the LTSpice circuit simulation file for David Johnson's 3 nano-ampere circuit here:
https://github.com/rabbithat/3nanoAmpOscillator

Edit2: I anticipate a potential problem though: the 3na oscillator has very high input impedance. PV cells are modeled as having a shunt resistance, and unless that shunt resistance is exceptionally high, then most of the generated solar cell current won't be entering into the oscillator but will instead be lost as wasted current through the shunt resistor. I'm hoping that doesn't preclude the oscillator from working, but it might if that reduced current translates into reduced voltage at the inputs to the oscillator. The best case scenario would be that the oscillator simply has a much longer cycle time with the PV cell as compared to a battery. In any case, shunt resistance doesn't seem especially easy to measure, so one strategy would be to just build the circuit and see how it works with the target PV cell rather than fuss too much over constructing an accurate equivalent circuit to plug into the simulator.

Edit3: Good news. Using the method published in IEEE to calculate PV shunt resistance (https://ieeexplore.ieee.org/document/1483817), I calculate the shunt resistance on the keychain solar cell to be 30,681,818 ohms. So, more than likely the oscillator will work when hooked up to it. This also finally explains why these solar cells perform so well at even ultra low lighting conditions.

This thread seems to have petered out, so I guess that's the end of it. It was nice while it lasted.

• Dear @NeverDie, you've done tremendous amount of work! The topic is extremely interesting, but I admit I can't keep up the pace, especially when discussion dived so deep and requires fair amount of research and simulation. Let's just keep it floating and open for everyone (I really hope David might kick it up). I personally try to follow up your recent posts a bit later, sorry

P.S. Asked a colleague about it and he's like: "Nano... what?!"

• @Mishka I recently had some convivial email exchanges with David Pilling after I reached out to him. He seemed interested in this thread, or maybe he was just being polite. Regarding his previous efforts, he mentioned that he was eventually able to run his PUT oscillator at 200 nanoamps.

• @Mishka I've got good news, and I've got bad news. The bad news is that according to the LTSpice circuit simulator, the Dave Johnson circuit, as given, is nowhere near 3na of power consumption. It's much higher than that. Here's what it shows as the current passing through the R10 resistor in the figure below:

The good news is that by increasing the resistance and capacitance, I've confirmed it's possible to run the oscillator at 1 lux on the keychain solar cell:

If measured at the output pin of transistor Q2, it produces a 2 volt pulse every couple of seconds:

I'm pretty confident it will run at even lower lux, al beit producing a lower voltage, but I'm not yet setup to test at less than 1 lux yet.
Here is an approximation of the modified circuit and its current consumption:

As you can see, both the average and the instantaneous current consumption are less than for TI's TLV5110 chip.

And yes, I've confirmed through testing that it can self-start at 1 lux even if it had been pitch black prior! In that case it starts a pulse train at lower magnitude but higher frequency and gradually works it's way up to the 2 volt magnitude at the 0.5 Hz frequency, which at 1 lux is where it settles.

• @NeverDie Oh, nice! You may eventually turn it out into a PWM/PFM charger.

• @Mishka The circuit is more stable and consistent than the 3v simulation would suggest. I'm now totally sold on the value of simulation, but it's a bit problematic when a solar cell/panel is involved because for an accurate simulation you need to find an accurate "equivalent circuit" to use in place of the cell/panel, and for accuracy that means a 5 element circuit: two diode, shunt resistor, series resistor, and a current source. However, figuring out the correct values for those parts requires a lot of measurements to get the desired accuracy and is a project in itself.

That said, I'm optimistic that there are some less mainstream transistors that will allow the circuit to run at lower voltage.

• Here's a courtesy heads-up.

I just now stumbled across a circuit:

published here:
https://www.edn.com/solar-powered-motor-runs-on-10-na/
that allegedly can operate on as little as 10na while collecting energy, which it then uses to power a small pager motor once a threshold voltage is reached.

It also has the virtue of utilizing inexpensive jelly bean parts and not relying on gigaohm resistors, which in the Dave Johnson circuit turned out to be so large that I lack the means to verify their specs through measurement after they are delivered.

This other guy instantiated the circuit as a PCB, and he made the gerber for it available as a free download: https://hackaday.io/project/159691-electron-bucket-extreme-power-management-module

If it turns out to be true that the circuit can both collect the current and trigger at a threshhold voltage all with just 10na of overhead, then on its face it sounds better than the David Johnson circuit turned out to be and possibly also better than many/most/(all?) of the commercial chips that we've reviewed on this thread if paired with an appropriate amorphous solar panel.

Edit:
But wait! There's more. There appears to exist an equivalent single chip voltage detector that also consumes a mere 10na of current: https://www.akm.com/content/dam/documents/products/power-management/power-ic-for-energy-harvesting/ap4405aen/ap4405aen-en-datasheet.pdf
It's itty bitty, so it's probably a great fit for your uber-compact design.

"But I want more!" I can hear you say. "I want a total step-up solution! And I want one that doesn't use a transformer!" Well, of course you do. Who wouldn't? Apparently, a 0.2v transformerless step-up solution does exist as well. I'm just not sure where. They developed it for a customer who wanted to harvest energy from... bacteria. Actually, the official term is "microbial fuel cell." The chip is the AP4470, and thankfully it can also be powered by solar, without bacteria.
https://solutions.akm.com/us/en/applications/energy-harvesting/
But can we buy it? Or is it just another inaccessible research project? I don't yet know. Can you read Japanese? The trail of bread crumbs written in English seems to run cold after the above link, but there's more about it that's written in Japanese. Argh.

• @NeverDie This. Is. Stunning!!!

I must admit that I were stuck with a CMOS driven circuit, but there are BJT circuits with amazing level of practicality. The decision to employ a LED is simply brilliant. I don't know shall we put it into a SPICE, perhaps to facilitate selection of real components, but taking in account the Hackaday project it should simply fall into place. Going to examine the project. It's definitely worth implementing it, thank you very much for finding the project!

The AP4470 looks very interesting too. With reported 7Β΅A current consumption when boosting starting from 0.2V, and fixed high to low output voltage from 2.6V to 3.55V, it looks like a strong competitor to the AEM10941. I'd still stick to the latter though, not only because of availability (including documentation), but the e-peas product also has very appealing buck-boost configuration.

I'm also thinking about even more modular design of the boards (details will follow later), so having two harvesting circuits targeting different scenarios is the right way to go.

Thanks again for your interest!

• ## Here's another one: https://patents.google.com/patent/US20170133938 He claims the startup power is just 100nW. For contrast, TI says their BQ255xx chip requires 15 uW. i.e. an entire order of magnitude more. Sounds too good to be true, doesn't it? Which leads me to wonder: just how well are patents vetted before they're granted? Might it still be granted even if the author never made a a circuit that performed anywhere near as well as the patent claims? Is anyone even checking?

By the way, on a different topic, this might interest you: https://www.mouser.com/ProductDetail/426-DFR0579 It's a \$12.90, 30mmx30mm, fully assembled breakout for the SPV1050, configured as a boost converter.

• Here's another one: https://patents.google.com/patent/US20170133938
He claims the startup power is just 100nW. For contrast, TI says their BQ255xx chip requires 15 uW. i.e. an entire order of magnitude more. Sounds too good to be true, doesn't it?

What's interesting about the circuit is that it uses the self-resonant converter together with a MOSFET (HEMT is recommended) which is closed at low voltage. There, the 1:1 transformer is used to bump the gate voltage and thus fully open the MOSFET when it reaches the threshold value Vth (the paper notices it at 120 mV, but for the a-Si cell it might be at 2.6V). The more it opened - the more voltage at the gate. This results in discharge of the input capacitor to the load until the gate capacitor voltage + the second inductor voltage won't drop below Vth. The input capacitor cut-off voltage could be configured to 1.8V so it will charge faster on the next cycle.

The patent mentions 0.1V x 1Β΅A = 1nW startup power. Upon charge of the input capacitor, the leakage current will be at about tens on nanoamps. Perhaps rest of the harvester circuit consumes something too. Obviously, when it's going to discharge the inductors will cut some efficiency, but it's worth it anyway.

Looks interesting!

Which leads me to wonder: just how well are patents vetted before they're granted? Might it still be granted even if the author never made a a circuit that performed anywhere near as well as the patent claims? Is anyone even checking?

Well, a patent is just an exclusive right to the invention, and AFAIK there is no practical consideration neither verification of the patent subject. All that's checked is the invention wasn't patented before.

By the way, on a different topic, this might interest you: https://www.mouser.com/ProductDetail/426-DFR0579 It's a \$12.90, 30mmx30mm, fully assembled breakout for the SPV1050, configured as a boost converter.

Yeah, it's nice! Thanks for the link! I think we here will be able to offer something interesting too: both boost & buck-boost combo board with USB and LDO, 25 mm diameter. Now in trendy corona-shaped profile from the OSHPark

Unfortunately, can't assemble them due to the quarantine

• (HEMT is recommended

Wait. He reccommended a PHEMT for part 315 and an E-PHEMT for part 445:

The self-starting oscillator 445 utilizes a transistor. In one embodiment, the transistor is an E-PHEMT (Enhancement Mode Pseudomorphic High Electron Mobility Transistor) transistor, as the switching device to form a resonant step-up oscillator using a coupled inductor (the left and right inductors, ratio 1:1, 1 mH) and a resistor and capacitor in parallel at transistor's gate. The self-starting oscillator 445 is in series with the inductors. The transistor is normally off at zero gate voltage which would be the case with the two solar cells in complete darkness. The transistor's threshold voltage is very low and has a value greater than 110 millivolts.

[0065]

The E-PHEMT transistor 445 can be described as having the combined characteristics of a FET (Field Effect Transistor) and BJT (Bipolar Junction Transistor) and is used primarily for high-speed RF amplifiers in cell phones or other communication gear, but it is also an excellent candidate for low voltage self-starting oscillators like the oscillator 445.

I'm confused. Aren't 315 and 445 simply different aliases for the same physical component? 315 at a higher abstraction layer and 445 at the detailed layer? Except... isn't an E-PHEMT different from a PHEMT? So, they aren't aliases for the same part after all? Or, maybe they are the same, but 315 refers to a different potential embodiment than 445? Or... do HEMT, PHEMT, and E-PHEMT all mean the same thing?

By the way, I mispoke in my earlier post. 100nW is actually two orders of magnitude lower than TI's 15uW cold start minimum for TI's flagship energy harvester. If the patented circuit now under discussion here really does perform as well as it claims, then that makes it all the more impressive.

If it needs 100nw of continuous power, then it's of little use to me. If, instead, it can draw the needed power from harvested energy stored on a capacitor--and then collapse after the cap power runs out--then, cool! That I could use.

If only there were a proper LTSpice simulation of the circuit already available....

Unfortunately, can't assemble them due to the quarantine

You mean their automated assembly is off-line, or that you can't source all the parts you need due to the quarantine, and so you can't DIY the soldering even if you wanted to?

BTW, I like your PCB homage to the caronavirus. Subtle, yet amusing!

• I'm confused. Aren't 315 and 445 simply different aliases for the same physical component? 315 at a higher abstraction layer and 445 at the detailed layer? Except... isn't an E-PHEMT different from a PHEMT? So, they aren't aliases for the same part after all? Or, maybe they are the same, but 315 refers to a different potential embodiment than 445? Or... do HEMT, PHEMT, and E-PHEMT all mean the same thing?

I see the components are numbered through all the figures in the form XYY where X is the figure number, and YY is the component number. Such, 115, 315, and 415 are referring to the energy harvesting circuit. The circuit contains x20 resonant DC-DC converter, and x45 do reference the transistor or crystal oscillator.

An enhancement mode transistor (N-channel MOSFET or an E-HEMT) is required because it has to be closed at zero bias.

By the way, I mispoke in my earlier post. 100nW is actually two orders of magnitude lower than TI's 15uW cold start minimum for TI's flagship energy harvester. If the patented circuit now under discussion here really does perform as well as it claims, then that makes it all the more impressive.

Oh, my, it's 100 times different, rght. I'm still not used to the numbers and feel that if we take a couple more steps, we will go to the quantum level

Unfortunately, can't assemble them due to the quarantine

You mean their automated assembly is off-line, or that you can't source all the parts you need due to the quarantine, and so you can't DIY the soldering even if you wanted to?

Just can't get to the soldering station, it's closed in the office with some other components until May.

BTW, I like your PCB homage to the caronavirus. Subtle, yet amusing!

All credits go to OSHPark which didn't bother to remove the panel tabs

• I'm still not used to the numbers and feel that if we take a couple more steps, we will go to the quantum level

LOL. In that case, strap yourself in Dorothy, because Kansas is about to go bye-bye: here's a voltage detector which claims to have a quiescent current of less than 6 pico-amps!
! https://www.bristol.ac.uk/media-library/sites/engineering/research/eem-group/zero-standby/UB20M_Datasheet_Rev.1.5.pdf
The only thing which appears to tarnish that claim is that it has a leakage current of 100 pico-amps. Even so, though, I'm not aware of anything else that even comes close to that. If it does what it claims to do, then I'm imagining we could harvest energy from even a very dark environment and yet still be net positive on harvested energy (without the control hardware consuming all of it and then some).

Unfortunately, their UB20X chip doesn't seem to be stocked anywhere. I sent an email to the company yesterday to inquire about how to buy it, but so far I haven't heard anything back yet. I hope they're still in business.

• @NeverDie Well

What can I say? Only that the PDF is here. They seem achieved this ridiculous leakage with careful transistor selection. Very nice!

• @Mishka Thank you very much for that link. Gosh, it sure would have been awesome to have such an ultra low power wake-on radio such as that described there. Unfortunately, I'm still getting no reply to even my second email attempt at contacting the company. Maybe they'll reply later, but for now I'm going to assume they are closed for business during the Caronavirus attack.

Fortunately, Figure 5 in the paper you linked shows an equivalent transistor layout for the voltage detector. It lacks a BOM with part numbers, but I'll nonetheless take a quick run at trying to simulate it in LTSpice--maybe I'll get lucky. If you were in my shoes, exactly which simulated transistors/mosfets would you be trying?

As for alternatives to the UB20M, the nearest I could find is this:
https://www.ablic.com/en/doc/datasheet/photo_ic/S5470_E.pdf
which, admittedly, isn't as nice because it is an ultra low current detector rather than a low voltage detector. Its quiescent current is higher than the UB20m, but it appears to be still quite low in absolute terms. What the S5470 does have that the UB20M lacks though is that the s5470 is well stocked at Digikey and similar places.

Have you run across any other parts that might fit the UB20M role?

Edit: I put Figure 5 into LTSpice. I could get it to generate the ~100mv reference voltage, but it doesn't appear to switch anything nor "detect" and then switch anything either. So, maybe there is more to the circuit that what they are showing. Given the circumstances of not being able to acquire their UB20M, it's a bit of a let down.

• The last option I can think of would be to try these special mosfets from Advanced Linear Devices:
https://www.aldinc.com/pdf/ALD110802.pdf
The gate leakage and drain source leakage combined is typically just 13pa. They can switch at around 0.2v, which, I suppose (?), could be viewed as a kind of voltage detector. Maybe in that sense, then, it even outperforms Bristol's UB20M? Also, unlike the UB20M, they seem to be relatively available through digikey, mouser, etc.

• Fortunately, Figure 5 in the paper you linked shows an equivalent transistor layout for the voltage detector. It lacks a BOM with part numbers, but I'll nonetheless take a quick run at trying to simulate it in LTSpice--maybe I'll get lucky. If you were in my shoes, exactly which simulated transistors/mosfets would you be trying?

That's true. The components selection is the hard part. I din't find anything, but the MOSFET arrays by ALD, and I see you've found them already.

It seems the most of discrete elements are tied to nanoamps and only few are diving to picoamps area. For example, the Nexperia settled it to 25 nA, as well as the TI does. But for some selected integrated circuits there are the picoamps, and some opamps may draw only femtoamps which is impressive. There is also the nice article on possible design issues - quite surprising - when building such a uber-low-power circuit - https://www.edn.com/design-femtoampere-circuits-with-low-leakage-part-one/

As for alternatives to the UB20M, the nearest I could find is this:
https://www.ablic.com/en/doc/datasheet/photo_ic/S5470_E.pdf
...
The last option I can think of would be to try these special mosfets from Advanced Linear Devices:
https://www.aldinc.com/pdf/ALD110802.pdf

Yeah, that's it. And the cool part is that the ALD offers 2V*200nA=400nW energy harvesters which work very similar to those we're trying to design here - http://www.aldinc.com/pdf/EH300.pdf

Unfortunately, still not sufficient to run your a-Si 80nA solar panel.

Edit: I put Figure 5 into LTSpice. I could get it to generate the ~100mv reference voltage, but it doesn't appear to switch anything nor "detect" and then switch anything either. So, maybe there is more to the circuit that what they are showing. Given the circumstances of not being able to acquire their UB20M, it's a bit of a let down.

It has to switch the VOUT on as soon as the VINL will be high enough to close the MN5 and pull down the VREF thus resetting the triggers and causing them to produce the VOUT.

I've put it into KiCad and immediately failed with component selection. In addition to issues with the search of a low-current MOSFETs, the ngspice has incomplete support for the modern PSPICE models. And create own models is a cumbersome task

After trial and errors I've ended up switching to ngspice internal models. After some trivial tuning the circuit started to work. I've just added input (storage) capacitor and have attached a simple load (switched with an additional N-MOS) to get the simple harvester work.

On VinLβ₯2V input capacitor is discharged to load R2 until VinL will drop below 1V. Both voltages are configured via MOSFET gate thresholds.

For details please take a look to the eeschema file - https://drive.google.com/file/d/1O8aVj7ZzjG1TNdTJOce4i2P65X-aRLgB/view?usp=sharing.

Voltages:

Input current I (via R1) in dependency of input voltage. I(R1) = 3V/100M = 33nA to simulate the a-Si cell.

I don't know how much current the circuit will draw in real life, but taking in account low voltage source (please note, datasheets mention 25nA as upper threshold) perhaps there are some chances to fit into the a-Si cell current budged.

• Have you run across any other parts that might fit the UB20M role?

The UB20M is hard to beat. But there's another sub-nanoamp option: https://www.vishay.com/docs/66597/sip32431.pdf

• Have you run across any other parts that might fit the UB20M role?

...But there's another sub-nanoamp option: https://www.vishay.com/docs/66597/sip32431.pdf

How would the vishay fit into it? Are you thinking you would switch it on-off using an ALD mosfet, or ...?

• @Mishka Nice work getting it to switch. If I'm reading your graphs right, though, it look as though we're back to the land of 10+ nanoamps as opposed to the ~106 picoamps or so of the UB20M voltage detector, even though you're using the same transistor circuit as they are?

• @NeverDie I've finally managed to make a readable image of the circuit. For our convenience, here it is:

The circuit self consumption is comprised of MOSFETs leakage current, and current required to charge the C1 capacitor. Regarding C1 the startup current may be arbitrary low, but sufficient to charge it eventually. After that it won't require too much to sustain the circuit. For this particular ngspce model (where MOSFETs leakage is really low) those are picoamps indeed:

Those 30nA you've mentioned in my previous post are due to charging the C2 storage capacitor and is actually limited by R1=100MOhm resistor installed solely to emulate the weak a-Si panel. I.e. for one gigohm resistor it will not go higher than 3nA.

Of course, the model itself is far from being optimal and could be improved.

• Have you run across any other parts that might fit the UB20M role?

...But there's another sub-nanoamp option: https://www.vishay.com/docs/66597/sip32431.pdf

How would the vishay fit into it? Are you thinking you would switch it on-off using an ALD mosfet, or ...?

I have no idea. Bipolar based opamps have similar characteristics, as well as the UB20M which seems build using FETs only.

• @Mishka Fantastic!

I tried replicating it in LTSpice, but no joy as of yet using just the generic LTSpice parts. The magic must be in those ".model" statements, which I haven't yet entered.

What value are you using for your input voltage? It seems that a lot of it is getting dropped across the 100meg resistor, leaving not much left over for most of the circuit.

• @Mishka First attempt with the ltspice directives yields just a flatline of about 1 volt at the output:

Perhaps I need to switch to the same spice as what you are using....

• @NeverDie Oh, right. For the voltage source there is the 3V pulse defined as follows:

`PULSE (0 3 20m 1u 1u 60 0)`

Reads like "start pulse from 0V to 3V, after 20ms timeout, 1us raise time, 1us down, keep it on for 60 seconds". This helped to examine how the circuit starts. But the circuit has to start with flat 3V input anyway.

All MOSFETs are defined with MOS level 3 model, zero-bias threshold (`vto`) set to Β±2 V, transconductance (`kp`) to 50 mA/V^2 to minimally reproduce a real transistor. Both drain and source has 1 Ohm resistance. Please note, the controlled NFET has lower voltage threshold at 1 V - this defines lowest VinL voltage. The rest of parameters can be derived from the ngspice manual, section 11.2.

I expect that the ngspice and the LTSPICE may have different directives to setup the circuit

Also, you may want to drop the C3, M8 and R2 thus leaving the circuit very similar to that one in the paper. The R1 still be used to limit input current, and the C2 will help to model raising voltage.

Also, does the `.tran 10k` means 10k milliseconds?

• Also, does the .tran 10k means 10k milliseconds?

Actually 10,000 seconds. That was just me throwing in a high enough number such that if there were ever to be observed an effect, I figure it would have shown up within 10,000 seconds.

I was playing around with an alternative to the original model, the better to understand how the original model worked, and I came up with something not as great, but maybe (someday, somewhere) it might be useful anyway if used as a trigger for one of the the ALD 20mv mosfets:

This is a voltage sweep simulation to show what happens at different input voltages. As you can see from the chart, the voltage on the output (the green line) stays pretty close to 0v up until it reaches around 22mv, at which point it it jumps up about 22mv in value. At that time about 6na of current is being conducted through R1 (the blue line in the graph), and so that is the total amount of current being consumed by the circuit.

20mv is the minimum that the LTC3108 can startup and function at, so that is why I'm focused at such a low value.

It's quite an easily adjustable voltage "detector": using smaller values for R2 leads to higher trigger voltages, as well as higher voltages on the output. Of course, they also lead to higher currents, so maybe not so relevant to the matter at hand. However, if you ever need a voltage trigger that you can set to any value in some other context where current draw is not such a pressing concern, this might be an option.

Also, about 2/3 the current is being consumed by R2. If there were some other way to get a similar effect, but utilizing even less current, then that would be an improvement. Perhaps that's what the Bristol circuit manages to do. Perhaps choking off the current by using a high value for R1 (as in Mishka's simulation) and using a semiconductor of some kind in place of R2 would do the business.

Edit: And just now noticing that by increasing the value of R1, the threshold for the detection voltage can be raised while keeping the current consumed in the single nanoamp digits:

In this case, with the higher threshhold, it might well be a useful complement to a 20mv ALD mosfet.

Edit2: Breaking out the resistance still further yields even more useful results: a larger transition voltage and even fewer nanoamperes.

These are just a few random attempts. A more methodical push would probably yield something better. I suppose trying it next with specific simulated components rather than whatever the simulator's generic components are would better inform whether a real world circuit could be built.

• Answering my own question, I designed a circuit using "real" mosfets from the generic LTSpice library and got a nice snap transition on a "voltage detector", all while drawing less than 300picoamps:

So, that's a simulated proof of concept. Now I just need to pull the trigger voltage down to a lower number, and I suspect that may involve using mosfets that aren't in the generic LTSpice catalog.

Edit1: Ignore this particular circuit diagram. It turns out to be reducible to a much simpler circuit that draws even less current. I'm leaving it posted as a reference point for my own project tracking, but if not for that I would delete it.

Edit2: Lately LTSpice has, more often than not, failed to converge now that I have it simulating "real" mosfets. As a result I've started to look into TI's Tina circuit simulator, which AFAIK is also built on a SPICE platform. Although it's too soon to draw completely fair apples-to-apples comparisons, my initial impression is that TI Tina is much, much faster than LTSpice and also much better at converging. I'll update if that opinion changes.

Edit3: I've upgraded to using NTJS3151P and NTJS3157N as the simulation mosfets because they have lower threshold voltages and mouser has SPICE models for them that are free to download. I'm not yet endorsing them though, because it's just too early to say. They are just my first attempt, and there may be (probably are) better choices to be found. I'm finding it quite easy to import SPICE component models into TINA TI. I notice that some manufacturers, like Diodes Inc., actually rank their SPICE models as to how realistic they are.

@Mishka Which mosfets are you simulating? Head's up: I'd encourage you to find some real world simulated mosfets (you'll have to eventually anyway), because I'm found that, at least in LTSpice, the generic mosfets behave much, much differently than the apparently real-world simulated mosfets. Not sure why that would be so, but maybe their idealized nature are a little too idealized to be realistic in these types of circuits.

TINA TI lacks the convenience of a voltage sweep like LTSpice has, so I'm using a very low frequency triangle wave to approximate it.

Edit4: I'm starting to make progress with TI Tina towards simulating the original (Figure 5) circuit:

After crossing the input threshold voltage, I can either get a steady high signal, as shown here, or by decreasing the value of R1 and increasing the value of C1, I can either make the output do a single sudden transition to zero volts, which then steadily rises afterward with increasing input voltage:

or I can make the output go into a rapid oscillation:

Tina TI has a preview mode, which is how I was able to spot the oscillation when the simulation progress had otherwise slowed to a crawl. Not sure, but maybe either the oscillation or else (more likely) VF1's sudden transition to zero at the voltage threshold on the prior plot might be useful for driving a charge pump or something?

Oh, and if it isn't already clear, the green line is the VG1 triangle input voltage (which I'm using to approximate a "voltage sweep") and the brownish-red line is the voltage measured at the VF1 probing point.

Salient Observation: The "regulated" voltage produced in this simulated circuit is around 700mv, not the ~100mv reported in the Bristol paper. I presume this has to do with the particular mosfets I happened to choose. Perhaps if I can find some mosfets that will produce the 100mv target reported in the Bristol paper, then the rest of the results will fall into place as well. I wish there existed a circuit simulator that could do a "component sweep" to automatically try out a bunch of different mosfets and see what their effects would be. It would gratly accelerate the process of identifying the most desirable component parts that could be used. Seems like it should be an "obvious" feature to have, and yet I'm not aware of any circuit simulators offering it.

Since 100mv is far below even the Vgs(th) of all the enhancement mosfets in both the digikey and mouser parts catalogs, this seems like yet another clue pointing toward the use of specialty mosfets, such as those by manufactured by ALD. Either that, or fets of a different type are being used.

Anyway, now that I have a circuit simulator up and working and producing results fairly quickly (unlike LTSpice), it's time to move forward. Hopefully ALD has SPICE models for their parts (yup, for a few of them anyway: http://www.aldinc.com/view-pdf.php). If so, then plugging those in to the simulator to check the effect would seem to be the next step. I'd wager it's either that, or else maybe there are subthreshold effects that the spice simulators aren't modelling accurately.... I discount the later possibility because, well, it's 2020, and surely by now EE simulation tools are pretty well evolved to account for subthreshold effects?

Edit5: FFS, their POS spice models (last updated in year 2004) won't load into TINA. Do they load into NGSpice?

Edit6: Well, using this: https://e2e.ti.com/support/tools/sim-hw-system-design/f/234/t/515230, I was able to fix ALD's stone-age spice file. And now it loads into TINA without complaint. But why the heck does it default to VTN=-0.037. I thought VTN was the threshold voltage for an n-channel mosfet, in which case shouldn't it be a positive number?

Edit7: Well, no answer to that question, but I can confirm that VTN is the threshold voltage.
Edit 8: Taking another look at the UB20M datasheet (https://www.bristol.ac.uk/media-library/sites/engineering/research/eem-group/zero-standby/UB20M_Datasheet_Rev.1.5.pdf), I'd have to say that the very low pico-amps static current number that's advertised is a bit misleading without the context provided by Figure 2,

which appears to show that the input must be capable of generating a couple of nanoamps at the threshold voltage in order for the voltage to be detected. So if, hypothetically, under particular lighting conditions a small solar panel could produce at most 1na of short-circuit current, it still wouldn't have enough to get detected no matter how large it's open circuit voltage. That said, UB20M still does appear to be the best of breed, if only it were available.

• @NeverDie Nice reduce!

AFAIU, the C1+M2 N-MOS will keep the trigger M6+M10 input low, and the output will turn high as soon as input voltage will reach the Vth threshold for the M10. Please note, the output will be limited by the R3=10g, so the circuit is kind of a voltage detector only.

Have you tried it yet? How about making it oscillating? Also, could you explain please, what the M1 does?

Please also note, for some reason the original network has the C1 protected with diode built into the MP3 P-FET. This probably should to be simulated with a diode rather FET. How do you think, why they need it?

• @Mishka I'm rethinking the global strategy to emphasize minimizing leakage currents above all else, even if it means accepting higher threshold voltages. It's tough, though, because none of the parametric search engines (like Digikey or Mouser) appear to allow mosfet searches based on leakage currents. It's in the datasheets, but not searchable as far as I can tell. And with tens of thousands of mosfets to choose from, there are far too many to methodically review manually. So far leakage currents of 100na to 1ua seem common, and I need to find some mosfets which are much, much less than that or else this project will be academic. Maybe there's a way to leverage that Vishay load switch you identified (https://www.vishay.com/docs/66597/sip32431.pdf). Not sure how to proceed at the moment until some suitable real-world low-leakage mosfets can be identified.

A FemtoFET would be at least some improvement over what's comon (http://www.ti.com/lit/ds/symlink/csd15380f3.pdf), but it still lists fairly large MAX leakage amounts with no indication as to what typical leakage might be.

Nexperia lists some low leakage mosfets: https://assets.nexperia.cn/documents/application-note/AN90009.pdf
but I'd like to find lower leakage than even those, if possible.

Ideally low leakage and low threshold would go hand in hand, as lower voltages generally imply lower leakages also, at least for any given mosfet.

• @NeverDie That's true, discrete transistors have not too thin parameters on paper. But assuming quite low voltages (about 3V) I'd expect those Nexperia and TI transistors may draw picoamps indeed. I think this is better to check with real devices. But assuming how small they are an evaluation board will be required. There are some, but it might be way cheaper yet more flexible to assemble such a module manually.

For convenience, the custom PCB may also contain circuit required to measure the leakage. Perhaps a low-leakage capacitor may be charged to some known value, then a MOSFET (or number of FOSFETS in parallel) would discharge it for some time, and then the voltage drop can derive leakage.

• @Mishka Perhaps of relevance to your last point, I found a fairly similar looking circuit to the Figure 5 Bristol paper UB40M circuit. Not identical, but I think you'll recognize some common features, like cutting off the feedback after a threshold has been reached and the use of n-channel and p-channel mosfet pairs configured as inverters:

It's a bit different in that it's an oscillator circuit (not too surprising, as I showed above that the Bristol circuit can be made to oscillate also), but what's comforting is the authors claim it consumes just 4.2picowatts.

However, having become a bit jaded by now, I do wonder whether that 4.2 picowatts reflects only the supply current or whether it includes the leakage currents as well. If it's the "all in" number, then maybe it's better than the Bristol design. I'm guessing that when they say their design minimizes "short circuit current," they are referring to leakage current (?), and if so, that would maybe be directly helpful to the problem of avoiding too much leakage currents in whatever discrete component circuitry you and I might settle on.

https://ieeexplore.ieee.org/document/7426716

• @NeverDie That's true, discrete transistors have not too thin parameters on paper. But assuming quite low voltages (about 3V) I'd expect those Nexperia and TI transistors may draw picoamps indeed. I think this is better to check with real devices. But assuming how small they are an evaluation board will be required. There are some, but it might be way cheaper yet more flexible to assemble such a module manually.

For convenience, the custom PCB may also contain circuit required to measure the leakage. Perhaps a low-leakage capacitor may be charged to some known value, then a MOSFET (or number of FOSFETS in parallel) would discharge it for some time, and then the voltage drop can derive leakage.

I spoke too soon regarding the femtofets: they're frickin tiny, at about 0.6mm^2. That's not good from the standpoint of minimizing leakage current:

Edit1: I couldn't find a SPICE model for either Vishay SiP32431 or SiP32432. I sent an inquiry to Vishay, but I don't have high hopes they'll produce one. It has great specs though, so thank you for bringing it to my attention. Prior to learning of it I had been using http://www.ti.com/lit/ds/symlink/tps22860.pdf, which I had found to be a very handy chip. Ironically, it doesn't have a SPICE model either! Gosh, what is wrong with these manufacturers? Are they really too cheap/lazy to spice model their own chips, or is there some other reason for not making SPICE models readily available for every product in their catalog?

Edit2: I've converted over to using the ALD "subtreshold" n-channel and p-channel mosfets. I had to hack the spice files to get Tina TI to import the spice models. Hopefully I was able to preserve their accuracy.

Edit3: What's interesting is that even after substituting the super sensitive ALD parts into the circuit, the trigger voltage remains about 700mv.

Maybe the 700mv is a reflection of the particular ALD mosphets that I included in the simulation. This was just the first attempt. Maybe different ALD mosfet choices would yield a lower trigger voltage for the circuit.

Edit4: I received a reply from Vishay regarding their load switch. It reads: " Unfortunately, we donβt have its SPICE model. Internally it is a P-ch switch, gate is injected with a constant current during turn on."

• Some modest progress. If the TINA TI simulator is to be believed, then this circuit:

delivers a very clean 1 second pulse at VF2 about once every 10 minutes while consuming an average of about 6na. The one big caveat though is that it requires a 2v supply voltage.

It's mainly noteworthy in comparison to TI's TPL5xxx timer, which consumes about 6x more current.

The main objective was to have a very low power timer circuit that could wake up infrequentlly to briefly invoke a conventional voltage detection circuit, which in turn could activate an energy harvester to process the energy captured and stored on a capacitor, provided there was enough charge on the capacitor to justify it. This does seem like a good step in that direction, though it would, of course, be preferable to have a circuit which consumes mere pico amps instead of nanoamps.

If nothing else it would perhaps make for a very low energy wake-up timer for a wireless sensor device. Alternatively, maybe it could form the start of a discontinuous charge pump circuit.

It would be interesting to build the circuit as a check on the simultator's accuracy and also just to see if it actually works.

Just a WAG, but I'm guessing that upgrading the circuit to use transistors which have a higher beta and reduced leakage currents will allow the circuit to still function while consuming even lower supply currents.

Edit1: Also, if I were to use gallium arsenide transistors (or whatever other transistors that have a lower forward voltage drop), it should run at a lower voltage. Perhaps a lower current as well? No idea, as I've never looked into gallium arsenide transistors before.

• Just a WAG, but I'm guessing that upgrading the circuit to use transistors which have a higher beta and reduced leakage currents will allow the circuit to still function while consuming even lower supply currents.

BINGO! According to the simulation, substituting transistors with higher beta reduced the average current to less than a nanoamp:

In this configuration, the pulses are separated by about 1600 seconds, which is about 26 minutes, once it gets going. Also, the minimum voltage is now just 1 volt, as compared to 2 volts with the earlier transistors. If there are transistors with even better beta, perhaps the current consumption can be dropped even further. What are some good transistors to try that have exceptionally high beta?

Edit1: Substituting the higher beta ZTX788B for the PNP transistor and increasing some of the other component values, I was able to drop the voltage to 0.8v and the average current consumed to around 200 picoamps.

For the first build I intend to use all through-hole components to better mitigate against leakage currents, so I need to find a high beta through-hole NPN that's as good or better than the 2SD2704 NPN used in the simulated circuit. If that goes well then I'll try a surface mount build for comparison. 2N5963 is available in through-hole and has a fairly high beta (between 1200 and 2200), but I see no spice model for it. Soon I may have to learn how to make my own transistor spice models so I can be free from this limitation.

I thought maybe Darlington transistors, because of their high beta, were a logical extrapolation of the results so far and therefore might offer the ultimate performance. I did make one attempt subtituting a BC517 darlington with 30,000 beta for just the NPN, but doing that I so far had no luck getting the circuit to oscillate. Maybe both the NPN and PNP need to be darlington's for it to work? Perhaps a BC516 PNP Darlington would be a good match for it, as it too has a minimum beta of 30,000.

Also, for troubleshooting, I need to find a way to accurately measure picoamps. I already own a uCurrent Gold, and according to its description (https://www.eevblog.com/product/ucurrentgold/) , if paired with a 5.5 digit volt meter, it can measure down to 1 picoamp. I just recently acquired an Amprobe AM-160-A 500,000 count multimeter, so hopefully that will do the business. Amprobe claims that the DC voltage accuracy is +/- (0.03 % rdg + 2 LSD). For such tiny currents I expect measurement noise may be an issue, so I'm only hoping for accuracy down to 10pa, which should be good enough for present purposes.

• @Mishka This paper is a breakthrough of sorts: http://blaauw.engin.umich.edu/wp-content/uploads/sites/342/2017/11/568.pdf

Using dynamic leak supression, that university team has proven in real hardware that they're able to power a Cortex M0 using just 240lux with just a teeny-tiny, itty-bitty solar cell ( 0.09mm^2)that they fabricated onto the MCU die itself:

No battery or supercap! It simply runs whenever there's at least 240lux light. The good news is that the DLS circuitry is just a variation on an ordinary ring oscillator, and it looks as though it would be easy to implement using discrete components.

I have a first attempt of it working in simulation, using ALD parts, which oscillates however fast or slow as I want it to while consuming an average of about 20pa. That much is like a dream come true. It needs improvement to get a better voltage swing and a lower supply voltage, but it's a promising start.

• @NeverDie Wow, my congratulations on making so much progress! Diving below 1nA is serious achievement!

The paper on the batteryless sub-nW Cortex-M0 shows a state of the art circuit built with FETs in super cut-off state. Thanks for finding it! But this makes me think that from all the networks we've considered here - the 3nA oscillator by David Johnson, the ready to use 10nA solar-powered motor driver by Stepan Novotill, and the UB40M chip by Bristol - due to some leakage elimination techniques a MOSFET based circuit might have the best performance anyway. The essay on femtoampere circuits also suggests FETs for lower leakage. (But I admit I still extremely impressed about those two BJT circuits.)

The relaxation oscillator with 230 fJ/cycle efficiency is also voltage driven, i.e. based on MOSFETs with proper threshold. Similarly to the UB40M it uses capacitors for time adjustment. By chance, detailed description is available for free as part of the Ultra-low energy electronics for synthetic biological sensors paper, please see chapter 3.

Components selection still play important part here, but assuming no femtoamp level I don't think package size will be too important. Enough clearance around elements may work similarly well. Regarding threshold values, the bigger voltage should be applied to the gate in order to close the transistor, the less leakage current between source and drain may be expected. This is exactly the reason why super cut-off state gates are working so well. The nice overview of this and other leakage elimination techniques described in the Design and Modeling of Low Power VLSI Systems book the relevant chapter from which is available as a dedicated paper. Perhaps it could help optimize current leakage later when the concept will be more or less ready.

The pragmatic question still how the desired circuit should work. I think the major finding was that a-Si cells are capable of high voltage in very low light conditions. This allows to avoid overhead and complexity coming from extra charge pumps or other regulators, and drive MCUs and sensors (usually working in 1.8V to 3.6V range) from a store capacitor charged directly from the a-Si cell. Another big advantage is that such a circuit will have nearly zero cold boot current.

How low should it go? The measured cell you use for experiments produce current in nanoamps, and when the cell current goes down to picoamps the voltage level seem also drops significantly. Also, waiting for the capacitor to charge from a picoamp source may take forever. IMHO targeting sources with few tens of nanoamps, and therefore maintaining the harvester self current less than 1 nanoampere should be considered a great success. Of course, the less quiescent current the harvester has - the better.

For such a low-power source I'd expect the energy will be harvested for a long period of time (tens of minutes), and then dumped it all at once into the MCU and a sensor. Using the collected energy to charge a battery is impractical: modern devices require microwatts of energy, and the harvester simply can not withstand the consumption. For online operation a conventional harvester like the AEM10941 should be used.

• @Mishka I'm flexible. Which circuit are you most interested in building? Let's try putting it together with real hardware and see if we can get it to work. If we can't, then we just move on to the next circuit and keep trying until we find a circuit that does work. Fair enough?

• @NeverDie More than enough

It seems there are two more or less working BJT based circuits which can be tested easily - the 3 nA oscillator which you've modeled with different transistors, and the solar motor project. Both are way more low-power than existing harvesters.

The FET based circuit remains in doubt until suitable components were selected. But IMHO putting some FETs to test to measure D-S leakage would surprise with numbers.

Regarding application, I have no requirement for so ultra-low power system, but many examples do measure something and then broadcast the data via BLE. They may even use harvesting switches, like the On Semi BLE-SWITCH001-GEVB evaluation kit. Maybe we can also consider something like this? If you have any good app on your mind lets aim at it.

• @Mishka Looking back over it with fresh eyes now, maybe the peak current rate matters no less than the average current rate. With the 200pa average transistor oscillator (above), there are some very short but significant current spikes that a weak solar cell that's not producing much current might not get past.

Perhaps better would be something like this nmos ring oscillator, whose current draw never exceeds 3.6na? For example:

I couldn't get this particular n-channel mosfet to oscillate at less than 3v, but maybe some other nmos would.

At this particular point I think I'm most interested in getting a DLS oscillator to work, first in simulation and then in real hardware. It may or may not be overkill, but it seems to hold the most potential.

But, of course, you're right: knowing the app would pin this down. I suppose right now I'm still getting a feel for what might be possible.

There might be some side benefits as well, such as perhaps schmitt triggers that don't pull a lot of current near their transition point:

https://books.google.com/books?id=BxX_DQAAQBAJ&pg=PA337&lpg=PA337&dq=leakage+optimized+schmitt+trigger&source=bl&ots=SpqKp_p2WK&sig=ACfU3U13AjqgaLMWrsxbKil79lsI4L6vKA&hl=en&sa=X&ved=2ahUKEwiN3NiZ0YXpAhUMP60KHeLEAGoQ6AEwCXoECAoQAQ#v=onepage&q=leakage optimized schmitt trigger&f=false

• but maybe some other nmos would.

... and I think I may have just now found that mosfet.

According to simulation, this oscillator consumes less than 25 picoamps at all times if running at 350 millivolts:

In fact, with higher resistor values, it will oscillate at even lower currents than that. Thus, even a solar cell in extremely dim light should be able to power it. Also nice: the same circuit runs at higher voltages if you want/need a larger voltage swing.

I think I'll order the parts and build it. Wish me luck!

• @NeverDie The circuit looks like a parametric oscillator indeed, and it is cool! What I like about it (of course, if I get it right) is that it employs only one transistor model, and those gigohm resistors are maintaining the current consumption really low. For this reason there is no need to carefully select the transistors - everything that has appropriate gate threshold value should work just fine.

On the other hand, it might happen that if you need it to work at higher frequency you will have to lower resistance of the R1-R3 and thus increase the current consumption.

BTW, accordingly to datasheet those particular FETs has quite high D-S leakage up to 1 Β΅A. But again, should not be an issue. Perhaps, while you're here and have tools to measure picoamps, you might be interested to grab a couple of those Femto N-FETs or other officially low leakage transistors, just to compare them to others. In particular, put them against a usual FET in the super-cutoff state, i.e. when supplying negative gate-source voltage.

And, of course, I wish you best of luck with this experiment and look forward for your updates!

• @Mishka I tried looking into the ultra low leakage Fets, like the femtofet, but they are just impossibly small:

If you know of any that are of a more manageable size, please do let me know. Partly it's just very tiny to handle, but also with the pads so incredibly close, I'm afraid there might be leakage outside the chip due to their close proximity.

I'm actually quite keen to try the Vishay SiP32431/2, but digikey and mouser don't have the larger package size (SC70-6) in stock, just the very small size packages. When that changes, I'll buy some to try. If there's some other source, I could try that.

• For this reason there is no need to carefully select the transistors - everything that has appropriate gate threshold value should work just fine.

You've highlighted an essential point, which is what I too had thought, and yet the simulations (and I'm using the SPICE models provided by the manufacturers of the MOSFET parts) indicate that its much easier to get some NFETs than others to oscillate in this particular kind of circuit. Give it a try yourself and see. And it turns out Vgs(th) alone is not a good predictor. Then it seemed Rds(on) was a good predictor, but I seem to have just recently found a counter-example to that. Let me know if you have any insight. It would be good to know what what makes for a good MOSFET pick. I hope it's not just a reflection of how good or bad the component models are. That is a big reason why I want to build something right away: to see if it's true or whether the simulations are poor fidelity. If the latter, hopefully not all of them are, and maybe there are some red flags I/we can identify in advance as to which models might be good and which not. Or, failing that, maybe some manufacturers do a better modeling job than others, and knowing in advance who makes good models would steer me toward picking their mosfets.

Unfortunately, one un-related finding I've discovered about this circuit is that high gigaohm resistors seem to be quite expensive! Who'd have thought that about resistors? I had assumed they would be dirt cheap, but above about 1 or 2 gigaohm the part price starts to rapidly rise.

Anyhow, from a practical standpoint, I'd rather not rely on high gigaohm resistances, because if those are used then suddenly the leakiness of everything (PCBs, insulation, practically everything) will likely become more of a factor in how the circuit behaves, and mainstream fabrication isn't geared up for that.

So I'll try building these circuits, even if I have to deadbug them, to answer the question about simulation fidelity, but then I'm hoping the next step will be low leakage components and/or leakage suppression by circuit design, such as DLS, because maybe then regular fabrication methods and materials will be good enough, and we'd be spared the cost of expensive resistors too.

P.S. I found a source that has SIP32431DR3T1GE3 in stock, so I ordered some. I think my highest hopes are now with that. Unfortunately, there are no SPICE models of it, but maybe tweaking down the DS leakage and GS leakage of a pre-built model for a different PFET would approximate it? After all, Vishay did say (in their response that I posted earlier above) that it is as largely a PFET. I also ordered some FemtoFETs, despite my reservations (above) about their incredibly small size--maybe we'll uncover DIY-friendly way to cope with that.

Edit1: Looking into it more, one of the differences between the nfet's is that some can oscillate when the resistor values are 1G and above, whereas others cannot. For instance, DMC2700UDM-7 is one that can't seem to manage it. It's "problem" seems to be that the voltage dropped across it is a lot less than the input voltage. Now, it does have a low RDS(on), but so does SiSA40DN (see circuit above), but SiSA40DN has a higher threshold voltage. Not sure if there are other factors, but apparently even with less of a current flowing through it, due to the higher resistor values, somehow SiSA40DN manages to not switch until more of a voltage develops across it. Not sure how to express that--maybe you do?--but I think that may be the crux of what makes it better in this type of circuit, because it's the voltage dropped across it which is what triggers the next nfet in the sequence. It would appear that there's some kind of relation between the VGS curve and the RDS curve which makes one NFET better than the other for this type of circuit. And when you think about it, the resistance across the nfet has to be a lot more than 1G in order for most of the voltage to be dropped across it, which means that the switching needs to happen at less than VG(th), which it does. So, perhaps it's the bias current flowing into the gate which is the critical factor? That would be controlled by the resistor value. Maybe DMC2700UDM-7 needs more bias current than SiSA40DN does, and so that's why it works only with resistors less than 1Gohm? I'm not sure whether or not there's even a datasheet entry for mosfet gate bias current (would it be gate resistance? gate capacitance? Total gate charge? Some combination of those? Is maybe gate-drain leakage a factor? Something else?), though I know for op-amps it's called out explicitly as an important figure of merit. Hmmm......

Edit2: It's confirmed. By placing simulator ammeters inline with the gates of the mosfets, it's clear that the gate on each DMC2700UDM-7 consumes 73pa in steady state, whereas the gate on SiSA40DN consumes less than 3pa. Also, during the transitions, the gate on DMC2700UDM-7 consumes around 900pa, whereas the gate on SiSA40DN consumes about half that. So, maybe that has something to do with with why DMC2700UDM-7 can't oscillate with gigaohm reistances? And, if so, what entry on the datasheet reflects that? Curiously, the source gate leakage in the reverse direction is far worse with the SiSA40DN (about 30pa) than with the DMC2700UDM-7 (less than 1pa).

• I think I likely found the smoking gun difference between the two mosfets. What's peculiar about them is that their Idss and Igss datasheet entries have values that are flipped with respect to one another:

I think I trust the Diodes Incorporated datasheet a bit more, because they supply more detailt about the issue:

whereas the Vishay datasheet is otherwise silent about it. If Vishay actually had a great DS leakage figure, wouldn't it have mentioned it in its intro paragraph? But no, it wasn't called out anywhere else in the Vishay datasheet.

The DS leakage of the DMC2700UDM-7 plays out in the simulation to its detriment, and I think it probably explains why the voltage drop across it is so low compared to the Vishay mosfet:

With the 1Gigaohm resistor in place, the DMC2700UDM-7 is showing a DS leakage of 2na, versus just 53pa for the Vishay. Quite a difference! The differences in voltages across the mosfets is equally striking (11mv vs. a full 2v), and, given the above test setup, I presume the difference is entirely due to the difference in leakage currents. With the gigaohm resistor, virtually all of the current entering the Diode's mosphet is lost due to leakage, leaving almost no voltage left.

I just hope the Vishay lives up to its billing and that their product delivers on what their SPICE model promises. I hope it's not a confusion that's been written into Vishay's SPICE model. However, right now, if I'm reading and interpreting it right, it looks as though the Vishay SPICE model results don't correlate with what the Vishay datasheet says: according to the Vishay datasheet, it appears that the Vishay DS leakage should actually be worse than the Diodes Incorporated mosphet's, but (as shown above) the Vishay SPICE simulation results don't show that at all. Instead, far from that, according to the Vishay SPICE model, the Vishay appears to be 2 orders of magnitude better. Meh, I'll be happy if it's so, but I'm starting to doubt it. Unfortunately, the much worse Vishay datasheet entry was measured at 30v, so it's not directly comparable to the Diodes's 20v, so maybe....? For sure, I'll be testing Idss on the real Vishay product, and then we'll know for certain.

• As a "Plan B," I tried simulating a ring oscillator using super-beta transistors, and the results are turning out surprisingly well:

The downside, as before, is that it relies on high gigaohm resistors to achieve the low current consumption, but the waveform nonetheless looks pretty sharp, and the frequency can be adjusted faster or slower by the capacitor selection. According to the simulation, at 2.5v, this one consumes less than 800pa. And, as you would expect, current consumption is less at lower voltages, but obviously then you get a less useful voltage swing.

Mouser sells some 1206 SMD 10Gohm resistors at \$1.18 each (quantity 10), but at 25% tolerance. I expect even a 25% tolerance is probably acceptable for a circuit like this, and so resistor cost need not be a show stopper.

I may actually end up preferring this circuit over the others. It seems like it may be a "good enough" fit for the solar cell that I'm using.

By increasing the ohms on the resistors feeding the resistor bases, you can increase the swing voltage even more:

That might be useful for using this circuit to control some other circuit.

To date I've had no luck getting any of the leakage supression circuits to work in simulation. It would help a lot if someone reading this could suggest a circuit to try--something more detailed than what's presented in the academic papers we've already identified.

• @NeverDie In SPICE the ring oscillator works just fine. I don't see why it may be hard to have it oscillating with any FET. However, due to the fact it's perfectly balanced (at least in it's current form) across all the three transistors it may be somewhat reluctant to start.

Here is how I get it in the light of the power consumption. For convenience, I've re-enumerated all components left to right.

Phase 1. I'm not going to cover the circuit boot and will start at the moment when the Q3 is closed. In the closed state VF3=0 it will tie the Q1 gate and the bottom pole of C1 to the ground. The Q1 is closed, and the C1 will be charging via R1 resistor. The R1 will set the charge time for C1.

At the same time, due to the closed Q3 the voltage source will be grounded via R3 and this results in extra leakage Vin/R3. At this phase, the overall current consumption will be about `I β Vin/R2 + Vin/R3`

Phase 2. The phase 1 will last until C1 will be charged to the Q2 gate threshold voltage. After that, the Q2 which was previously open due to the C1 voltage drop, closes, and this will tie VF2 to the ground and open the Q3.

The opened Q3 will shift ground level for the C1 thus doubling the VF1 voltage. The C1 will start discharging down to zero until VF1 won't balance VF3. Actually, the C1 it will be charged from the opposite side via R3. The R3 defines period of the stage 2. Consumption current should be about the same `I β Vin/R2 + Vin/R3`. Please note, since the Q2 is not participating in C1 charge/discharge it should be safe to keep R2 resistance much higher than R1 and R2, like 300g or so, and decrease the circuit consumption.

However, it seems slightly more complicated than that. Due to FETs non-linearity, at marginal gate voltages there is some drainβsource resistance. Despite the Q1 is open with VF3 voltage, it's not enough to have the C1 grounded, and this is why the circuit works at all. Instead, both C1 and the voltage source will be leaking via the Q1. While voltage source is limited by R2, the leakage for C1 may be quite high and require extra attention. Luckily, this is not true for the SiSA40DN - the C1 slowly discharges via Q1 and this compensates for leakage from the voltage source via R1.

Repeat. Upon C1 discharge it's going to close Q2 and raise gate voltage on Q3. The Q3 opens, VF3 voltage drops, then Q1 closes too, and the C1 starts charging back again.

Well, as for an astable oscillator the circuit looks cool, definitely would be interesting to build. But for energy harvesting purposes I'd prefer some UB40M variation - IMHO it's much cleaner from the point of parasitic leakages. Especially if taking in account those leakage optimization techniques like we've seen for the super cutoff gates.

• But for energy harvesting purposes I'd prefer some UB40M variation - IMHO it's much cleaner from the point of parasitic leakages. Especially if taking in account those leakage optimization techniques like we've seen for the super cutoff gates.

That's what I originally thought as well, except I haven't been able to get any of the leakage optimization techniques to work. That's what has driven me down the current path of seeing if I might be able to do anything worthwhile with simpler circuits like these. I didn't want to take this detour, but at least I could get them to "work," at least nominally. If you can see how to implement the leakage optimizations, and get them working in simulation, then that would be great. I'd love to see it. I'd much rather use some kind of smart leakage suppression circuitry than rely on super high gigaohm resistances. I've tried, but I just haven't been able to get any working circuits with that approach. TL;DR: I'm stuck wrt leakage suppression.

So, if you're able to make some headway on leakage suppression, I'd be more than happy to circle back to it.

BTW, a couple of interesting things about the NPN ring oscillator are worth mentioning:

1. It works over a wide voltage range: from 300mv up to 20v.
2. In contrast to the NFET ring oscillator, where when an NFET is "OFF", it continues to leak current, in the NPN ring oscillator, when the NPN is "OFF", it leaks almost no current at all--maybe just a couple picoamps or less.

Here are the waveforms and currents drawn when it's powered with just 300mv:

As you can see, in this particular example, where it is using "only" 10G resistors, it's drawing a sum total current of less than 70pa at all times.

• @NeverDie Regarding components selection - unfortunately, that's true, too few manufacturers provide that data in a table to compare and select from. So far we have the FemtoFET series from Texas, the FETs listed in the Nexperia's AN90009 paper, and the ALD FETs. General recommendations for a low-lakage FET may be:

• Higher gateβsource bias voltage. Obviously, the higher voltage required to turn a FET on - the more resistance between gate and source, and the less leakage.
• Higher source-drain resistance when on. It simply means the FET will have higher resistance when closed too.
• Protection diode may also cause some leakage.

However, an attempt to select low-leakage FETs using these recommendations will certainly fail. It rather seem more depends on specs a manufacturer tries to warrant. For example, in theory high drain-source voltage may imply lower leakage at low voltages. But usually lower power transistors are leaking less.

Such, all Vishay specs I've read for more or less matching transistors mention exactly the same values for GS and DS leakage. Similarly, all ALD transistors have very low leakage because the ALD is working hard to manufacture them so. But I admit, for unknown reason any of those low-leakage FETs are ridiculously small, it's very rare when any dimension is bigger than 1mm.

Looks like if we really want it low, we must accept the size. On the other hand, some youtubers do solder even 008004 which are way smaller.

Alternative way is to choose a couple of transistors and measure them. I think that 1Β΅A leakage from datasheet will barely go over 10nA in practice, so your choice should be just fine.

BTW, SPICE models usually operate with physical dimension, so should be accurate enough when it comes to comparing leakage of different items.

• a couple of interesting things about the NPN ring oscillator are worth mentioning:

It works over a wide voltage range: from 300mv up to 20v.
In contrast to the NFET ring oscillator, where when an NFET is "OFF", it continues to leak current, in the NPN ring oscillator, when the NPN is "OFF", it leaks almost no current at all--maybe just a couple picoamps or less.

Yeah, it is impressive, no doubt. I'm not confident with so low-power circuits and were taught that MOSFETs are leaking less, and BJTs are requiring more current to drive. But this discussion disregards it all, at least when it comes to discretes

• While i wait for parts to arrive, I crafted a simple "Hello World" variant of the circuit to blink some LED's so as to have an easy first test ready when setting up real hardware:

• Because I didn't have 1000uF capacitors laying about, I built a variant to the test circuit (the one directly above) to match what I did have on hand. Bottom line: it works, and,equally important, AFAIK it seems to work in the way that the simulation predicts.

In order to light the LEDs, the test circuit was deliberately designed to draw many orders of magnitude more current than the ultimate low energy target oscillator. Purely out of curiosity I hooked it up to various solar panels anyway just to see how it might behave under different lighting conditions. Not surprisingly, when there's adequate power, it oscillates and does what you would expect. However, when starved of enough current, it stops oscillating but nonetheless lights all three LEDs with whatever current it does have. Then, if the lighting improves, it will gradually start oscillating again. Neither here nor there, but, at least conceptually, I'd rather that it instead conserved its energy and didn't light any LEDs at all when it couldn't oscillate rather than light all of them. That way maybe it would be able to store up enough energy to resume oscillation, even if only briefly. That said, I don't expect this to be much of an issue in the ultimate target circuit, because its oscillation energy requirements should be many orders of magnitude lower, but at least now I know it's something I should probably look out for, just to be sure.

• @NeverDie Cool!

A supervisory circuit will be needed between the store and the load anyway. BTW, most of ultra-low power supervisors will consume tens of nanoamps. Does it mean it has to be a low leaking FET?

• @NeverDie Cool!

A supervisory circuit will be needed between the store and the load anyway. BTW, most of ultra-low power supervisors will consume tens of nanoamps. Does it mean it has to be a low leaking FET?

That's why I'm hoping that this will fill the role of supervisor:
https://www.ablic.com/en/doc/datasheet/photo_ic/S5470_E.pdf
The datasheet says it consumes <= 100pa of current, which beats even the UB20 (after the UB20's leakage currents are accounted for). More importantly, unlike the UB20, it's well stocked at both Digikey and Mouser, so getting it isn't problem. Unfortunately, AFAIK, there's no SPICE model for it. I'm hoping that something designed to detect faint signals won't be overly interfering, but I don't think we can know for sure without giving it a test drive. How it behaves during a detection event might also matter.

If the Vishay load switch could function as a supervisor, then maybe it would be even better. It seems worth looking into. For one thing, it's cheaper. Maybe it might even consume less current, either before or during a detection event.

Ultimately, the challenge may be how well the supervisor reacts to a very slowly rising current or voltage. All of the gigaohm oscillator circuits that are the current focus are current starved, and probably for that reason none of the oscillator circuits appears to switch very quickly. We know, for example, that a generic schmitt trigger tends to draw a lot of power near the trigger point. You mentioned a FET, but I suspect it would have the same issue as a schmitt trigger.

Unless you can think of a way to somehow roll-your-own ultra low power supervisor, I'm not aware of anything else. I suspect that maybe the Michigan team that built the Cortex M0 with the ultra tiny solar cell could easily beat both the ABLIC and Vishay supervisors--I'm still gobsmacked by what the Michigan team accomplished-- but at the moment I don't understand how to do the kind of leakage supression that's the foundation of what the Michigan team did. On my one and only attempt, after toying around with it, I was able to get one simulation that seemed to oscillate under very narrow conditions without meaningful leakage, and at first that gave me some hope. However, at the time I didn't see a way to extend that tiny, somewhat dubuious success toward anything useful. Having read the Michigan paper, can you get a leakage supression simulation working, either from their schematic or from one of the other papers? If so, that would be enormously helpful. I could post the simulation that I tried if you wanted to take a stab at it. It's not much, but pretty much anything, even an unremarkable crippled anything, is more than what typically gets published in the academic papers.

As for me, my next step is to fabricate/install some teflon mounts for my first attempt at the target circuit to rest on. I also need to build some fancier op-amp circuits to take measurements. It's a bit exotic, and maybe there's a better way, but at the moment this seems to me like the most promising path toward getting a verified working POC, or at least the low energy oscillator part of it. I don't think the SPICE simulations even attempt to account for noise, and so I have no way of judging in advance whether or not noise, at the projected ultra low power levels, might be a big or small issue or even no issue at all. I suspect it may require shielding though, and, if so, maybe that will be sufficient.

• The TS12001 looks like it could be incredibly useful, even just by itself. It behaves like a combination voltageDetector+loadSwitch. When below the threshold voltage, it disconnects the load and cuts its quiescent current to just 100pa: https://www.mouser.com/datasheet/2/761/Semtech_06142018_TS12001_Rev_1.5-1371249.pdf

Edit1: Unfortunately, I can't find anywhere that has it in stock.

• Unless you can think of a way to somehow roll-your-own ultra low power supervisor, I'm not aware of anything else. I suspect that maybe the Michigan team that built the Cortex M0 with the ultra tiny solar cell could easily beat both the ABLIC and Vishay supervisors--I'm still gobsmacked by what the Michigan team accomplished-- but at the moment I don't understand how to do the kind of leakage supression that's the foundation of what the Michigan team did. On my one and only attempt, after toying around with it, I was able to get one simulation that seemed to oscillate under very narrow conditions without meaningful leakage, and at first that gave me some hope. However, at the time I didn't see a way to extend that tiny, somewhat dubuious success toward anything useful. Having read the Michigan paper, can you get a leakage supression simulation working, either from their schematic or from one of the other papers? If so, that would be enormously helpful. I could post the simulation that I tried if you wanted to take a stab at it. It's not much, but pretty much anything, even an unremarkable crippled anything, is more than what typically gets published in the academic papers.

IMHO this is the promising direction to go. I haven't analyzed the circuits yet, but the super cut-off idea is dead simple - instead of grounding transistor gates, they have to be under-driven with a negative voltage. This should effectively remove free electrons from the depletion region and hence minimize drainβsource leakage. Unfortunately, this requires to maintain an additional negative power source which may draw it's own current to operate. The overhead may be to expensive for a circuit with few gates, but seems well worth it for a processor core with thousands of transistors. What's good, is that this technique clearly separates optimization from the logic. In SPICE it might be easily simulated with a second voltage source, for example, at -0.1V. BTW, for the same reason the higher Vth - the lower DS leakage should be expected.

I'm thinking about building the UB40M alike circuit with any transistors. Well, the FemtoFET series is very small indeed. But size of the biggest package codename F5 is 0.73x1.49 mm which is roughly the same size as 0603 components. With proper PCB footprint soldering them should not be an issue. All in all, what must we expect from a modern high performing transistor?

Unfortunately, my ngspice doesn't work well with the Level 7 model the TI provides. So to have anything tangible to play with I've noticed a complimentary pair from Vishay, Vth=2.5V, Vds=150V: SiA485DJ (P-channel) and SiA446DJ (N-channel). PowerPak SC-70 package also looks appealing - 2x2 mm will help save PCB space, but still not microscopic.

Unfortunately, the P-MOS has no SPICE model, damn it. I'll try to replace it with Si1411DH which parameters looks very close to the SiA485DJ, and there are SPICE models for it.

Some leakage curves for the FETs in the 0...5V range:

Interesting, that the faster raises the voltage - the more leakage occurs. For example, the same chart for 1s raise:

• @Mishka Great! I'm really looking forward to it. If you can get something working in your simulator then as a cross-check I can try replicating it in the TI Tina simulator. If it works in both simulators, then I would imagine the odds are that much better that it will work in the real world with physical hardware.

Speaking of simulation, I polished the ring oscillator circuit a bit more and, as a "virtual POC," got it to do pretty close to what I had originally aimed for:

In a nutshell: 1. When the timer switches on, it drives an LED (which represents a load ) with with up to 26 milliamps of current,. 2. When the timer switches off, it draws less than 500 picoamps until it switches on again, at which point the cycle repeats. The length of the period can be adjusted by selecting a different capacitor value. The idea is to leave the load switched off long enough to charge a capacitor from a tiny solar cell, enough that when the timer switches on there will be ample current available to drive the load. Obviously, the timer needs to consume even less current while OFF than the harvested current or else there won't be enough charge accumulated to drive the load when the timer switches on. Thus, keeping the sleep current extremely low provides a lot of headroom so that a meaningful charge can be accumulated during the sleep cycle, even if it the harvested light is quite dim and/or the solar cell is quite small.

• @NeverDie Congratulations! Looks very holistic. The only model needed is 2SD2704 - cool!

I'm unsure though will it be possible to substitute the star from three 100 pF capacitors with a single one 68pF?

Could you also isolate T4 and T5 from the oscillator, please, so the AM1 won't measure their leakage? It's interesting to compare that cascade to a MOSFET.

• @Mishka How would you like to see them connected? I'd be happy to re-run the simulation in whatever circuit configuration you like.

• Could you also isolate T4 and T5 from the oscillator, please, so the AM1 won't measure their leakage? It's interesting to compare that cascade to a MOSFET.

Maybe this kind of separation better answers your question about the leakage?

AM3 breaks out the timer leakage into T4 as a separate line item so you can more easily compare it to what the leakage of a mosfet would be.

• Yup, your proposed capacitor simplification works:

Thanks! Nice catch.

• Maybe this kind of separation better answers your question about the leakage?

Definitely. Thanks a lot!

It would also be interesting to know measurement from the AM4 when the LED driver circuit is off. You see, MOSFETs are mainly characterized by the subthreshold leakage current between D and S - the AM4 has it.

• It would also be interesting to know measurement from the AM4 when the LED driver circuit is off. You see, MOSFETs are mainly characterized by the subthreshold leakage current between D and S - the AM4 has it.

Glad you asked, but it turns out not to be happy news. As it stands, it's a very constant 28.73ua leakage, which is obviously pretty terrible.

That part of the circuit should have a big sign hung around it which says "insert something better here." There is no SPICE model for the ABLIC, but with some tuning maybe it could go either there or else just prior to an NPN transistor GND connection in the timer circuit. Some of the leakage currents at the transistor GND connections reach below 1pa, and IIRC, 7pa is the current at which the ABLIC would trigger during an upswing. If putting the ABLIC faint signal detector there doesn't change the circuit dynamics, then it will be slam dunk.

• Glad you asked, but it turns out not to be happy news. As it stands, it's a very constant 28.73ua leakage, which is obviously pretty terrible.

The circuit has so low leakage mostly due to the gigohmic resistors. In particular, those 300 pA bumps on AM3 may be due to the R4 limits (3V / 10 gOhm). And it looks like the right thing to do for a BJT. Oppositely, MOSFETs can be used as ultra strong resistors themselves. I.e. should you put several in series and the leakage drops.

I.e. it might be reasonable to drop a MOSFET in the place of T5+T6, and yet another gigohm resistor will cut the T4 leakage down.

• @Mishka Good idea.

Also, the above circuit was a run-up to putting the timer circuit together on a protoboard, but without teflon standoffs. I had originally planned to put the timer circuit on teflon standoffs to better ensure that it works, but then I realized that if PCB leakage turns out to be a problem, it might still work, but just need more light than if leakage isn't a problem. Or, maybe not: if the leakage is more pronounced in one part of the circuit than another.... So, I figure it's worth a quick and dirty first pass to get a feel for how well it will or won't work without the teflon, and for that rough-and-ready purpose I'm not too worried about the 28ua. Afterward, though, I definitely will care, and if you think of any other suggestions, they're always appreciated.

Edit1: CORRECTION: The treshold current for the ABLIC is 700pa, not 7pa. I guess that's good news, because it should be relatively easy to slip in underneath that. More precisely, what the datasheet says is that it detects 0.7nW (i.e. 700pa at 1v), so for higher voltages the threshold current should be proportionately less.

• @Mishka At the "big picture" level, I like TI's approach:
http://www.freepatentsonline.com/y2019/0028089.html
because it cleanly divides the problem into separate pieces:

1. Generate an ultra low current. In my case I'm doing that with Gigaohm resistors, but in their case they have an ultra low current generator circuit. I like their approach better, because the current remains constant over a fairly wide range of input voltage. The ultra low current buys time because it takes capacitors longer to charge (an/or you can use smaller capacitors), and it controls leakage by brute force: no matter what, the rest of the circuit is physically unable to leak more current than it's supplied. Presumably, if I had an ultra low current generator circuit then I could delete the gigaohm resistors in my circuit du jour and use it instead. Also, if it were a constant current generator, then presumably the switching near the threshold would happen faster, because you aren't waiting on an exponential decay timeline, as is the case with charging a capacitor with just a voltage source and a resistor. Instead, the capacitor voltage would change in a linear timeline.
2. Make a currenet starved Schmitt Trigger inverter. Well, that's TI's twist on the subject. I suppose the "Schmitt Trigger" part is actually optional. Fundamentally, just getting a current starved or leakage suppression inverter to work is the core of the problem. A paper I read suggests that the betas on the nmos and pmos may need to match.
3. Combine #1 and #2 and, Voila, make a ring oscillator. Presumably this will be the easiest of the three steps.

• I had a chance to try both the ABLIC faint signal detector and the Vishay load switch.

Originally I had thought the ABLIC was meant to be a current DETECTOR, but it turns out not to be so in the way that I had thought. Rather, it's more like a current SINK that will sink any and all current presented to it and that will switch if the POWER that's sunk is great than 0.7 nanoWATTS. So, the notion of putting the ABLIC between an NPN transistor and GND in my BJT oscillator circuit isn't going to work, because at that point in the circuit there's very little voltage remaining to drive the current, and hence, not enough power to turn on the ABLIC switch.

It could be made to nominally work if it's supplied with enough power (0.7nW or greater), but 0.7nW is actually quite significant in relation to my BJT oscillator circuit's power consumption. At least it's an option though.

I think the best way to run the ABLIC would be with short but infrequent pulses, because then its current drain could be amortized over the entire cycle. It would need to latch if triggered so that the detection could persist beyond just the short pulse. If the ring oscillator were also made into a charge pump, then I would guess that the the entire setup could be used to detect lower voltages. Perhaps something like:

• I had planned to use a uCurrent Gold with a 500,000 count DMM to measure currents below 1na, but there's simply too much variation in the voltage reading depending on how close I am standing to the DUT to get meaningful measurements. The problem appears to be the multimeter test leads. Even just moving my hands near them changes the measurement. It's not that it's noisy (moving up and down and all around). Rather, it shifts around depending on where I am standing in relation to it. Do I need special test leads, or will I need to use something else (either an o-scope or a specialized circuit) to get a measurement without this problem?

Or maybe it's static electricity and I need to earth ground everything, including myself?

Edit1:
Reporting back: I put everything on an anti-static mat and earthgrounded both it and myself. That cleared up my multimeter going bonkers, at least when it wasn't connected to the DUT. Right now it appears that the Vishay load switch, or more likely my mounting of it, is what's amplifying static electricity or some other stray voltages. So, I'm going to take another pass at grounding the adapter board I soldered it to and removing residual flux to see if that helps at all. Adding a bypass cap will also likely help.

I suspect that a better quality anti-static mat might be worth a try. The one I'm trying is brand new, fresh out of the box, but it doesn't have the conductive rubber like the more professional ones have. Also, the wrist strap didn't work well at all. I got better results from leaning my skin against the mat. Perhaps I need a conductive gel for the anti-static wrist strap to work better? And I don't have a conductive anti-static floor mat, so that's also a weak link in the current setup. Perhaps I should just remove myself from the equation and do the measurements remotely, via wireless link?

Edit2: I tried all of the above (short of getting proper conductive mats), and it all seemed to help, except in the case of the uCurrent Gold. Maybe because it has it's own virtual ground? In any event, I'm not confident I can get better than 1na resolution out of it if I'm physically anywhere near it. I think I would likely need more specialized instrumentation, perhaps remotely operated, to get decent sub-nanoamp measurements.

Edit3: Using a sticky gel electrode pad from a TENS on my wirst insead of an el cheapo plastic wrist strap seems to be a big improvement in terms of grounding my body. I presume it's because the TENS pad makes for a better connection (more conductive interface) between my skin/body and ground.

Edit4: I posted this picoamp uCurrent Gold problem on eevblog:
https://www.eevblog.com/forum/beginners/static-control-requirements-for-picoamp-measurements-using-ucurrent-gold/new/#new
so hopefully that will produce some informed insight/advice.

• As a ballpark, I'm starting to doubt it's worthwhile to target solar sources which produce less than 7na under dim light. Even if 100% of the current could be harvested without any declines, it would take 8 hours at a constant 7na rate to charge a 100u capacitor from 0 volts up to 2 volts. At that level, I'm sure I can get a wireless node to send or listen for enough packets to be interesting.

I'm estimating my supervisory overhead, if successful, may come out to around 1na. So, in all likelihood, the "worthwhile" lower bound for solar harvesting will be somewhere in the 1na to 7na range for a wireless node. A realistic lower bound would most likely be an even higher range to account for inevitable inefficiencies.

My keychain solar panel can produce 88na (short circuit current) under 1 lux lighting, give or take. So, when it's finally all put together, I guess the only thing that's going to vary will be just how dim it can all still function at.

On the other hand, if the light is reasonably bright, then even just a single photodiode may suffice as a worthwhile power source. In that case the entire device could, in theory, be ridiculously small.

Still, I suppose the most conservative answer comes not from how much energy is required to charge a 100u cap from 0 volts 2 volts, but rather in how much energy is required to sustain that level (while accomplishing at least some minimal amount of work) once it has been achieved. In that case, the minimum harvested energy would just be the supervisory overhead plus storage capacitor leakage plus the energy required to , say, power up an MCU and send one packet once per 24 hours. All the MCU's currently on the market that I'm aware of consume more than 7na even while turned off, so the MCU would need to be turned off by a load switch, or in some other way by the supervisor, to eliminate even that minimal level of drain.

For that reason, I tried measuring the quiescent current of the Vishay load switch using the uCurrent Gold, which is when I ran into the picoamp measurement issues. The measurements I got were all over the map, but they were all less than 1 nanoamp.

That's an outline for getting the most aggressive answer. To finish the calculation I'll need to measure the total energy consumed by a wireless MCU powerup cycle, and that will depend on the particular wireless MCU that's chosen. That in turn will inform whether sleeping the MCU will actually consume less than a full power cycle. In the case of an atmega328p and an RFM69, the combined sleep current is 200na, but that alone doesn't account for the energy expended waiting for the radio's high speed oscillator to come up to speed and its PLL to engage.

Here's a benchmark for comparison: A 5x4mm PIN diode can produce as much as 45ua at an open circuit voltage of 320mv: https://www.mouser.com/datasheet/2/427/vemd5080x01-1767531.pdf
Boosting that to 3 volts might yield 3 to 4 microamps at that higher voltage. Accumlating that electricity over time means that, at least in principle, the entire wireless node could be 5x4mm in size, or even smaller if a smaller PIN diode were used..

• There's another class of component that might bear looking into. In December 2019 Omron released:
https://omronfs.omron.com/en_US/ecb/products/pdf/en-g3vm-21mt.pdf
which is a MOS FET Relay that, when switched off, has a maximum leakage current of 1 picoamp. This is a solid state relay, not a mechanical relay. That kind of performance comes at a cost of about \$30 per device. However, maybe something not quite as state of the art would still impress at a more favorable cost? I can't say, as I haven't explored the category. I might be happy with with even 100pa leakage, especially if it were available at a much lower cost.

• The next test circuit I'll build will be this one:

On VF1 there's a nice 3 volt voltage swing. It's just a small step and will consume around 8na. Not enough current though for blinking LED's to know whether or not it's working, so I configured an MCP6022 as a voltage follower that I'll hook up to VF1 to confirm whether it's working as expected. The MCP6022 voltage follower should have an input bias of around 1pa, so it shoud not disrupt the circuit. If it shows the circuit is working as the simulator predicts it will, then I'll connect the Vishay load switch to VF1 and see if the circuit still works. If so, then the next step will be to swap the 10gohm resistors for 50gohm, and the 1gohm for 10gohm. That will take the total current drain to below 1na. If the circuit still works with the Vishay load switch connected, then bingo. If it doesn't, then I'll need some other low power way for the oscillator to drive a load.

Another possibility would be to build a ring oscillator out of the Vishay load switches. I can't think of any reason why that wouldn't work, and it would kill two birds with one stone. Because it seems so promising, I may even try it before the above. The only drawback is that because of no spice model, there's no way to simulate it prior to building it.

Edit1: Here is the MCP6022 voltage follower:

I air-wired all the connections and UV-glued both the chip and the wires to the protoboard so as not to strain the DIP pins. The protoboard is supported by 1 inch nylon stand-offs. This was the first-pass. I will add some bypass capacitors to polish it off even though initial testing indicates it works well enough without them. It's a two opamp DIP. The sensed voltage (orange wire) feeds the first opamp, which then feeds the input of the second opamp via the white wire. It's the output of the second opamp (yellow wire) which you then measure with your DMM. The red wire is the supply voltage, and the black wires are GND.

Edit2: The question of the moment is: how best to make the low leakage Vishay load switch into a low leakage inverter? One idea would be to have it drive a low-leakage p-channel jfet, such as perhaps the J177, which has a max cut-off voltage of 2.5v. Are there any p-channel mosfets with a lower max cut-off than that? According to the J177 datasheet, the drain cut-off current will be less than 1 nanoamp at a DS of 15 volts, so presumably much less than 1na at lower DS voltages.
Edit3: Looks as though J270 will be better: it has has a max drain cut-off voltage of 2.0v.
Edit4: Although it's an n-channel JFET, the 2n4118 sounds interesting. According to the datasheet, its typical leakage is just 0.25 picoamp at a Vgs of 20 volts: https://www.mouser.com/datasheet/2/676/jfet-2n4117-2n4118-2n4119a-interfet.r00-1649084.pdf
It also has a -1.8v cut-off voltage, so slightly better in that department. It doesn't indicate an Ids leakage current though.

Maybe better is the 2N4339:
https://www.mouser.com/datasheet/2/676/jfet-2n4338-2n4339-interfet.r00-1649114.pdf
It has a cut-off voltage of just -1v, an IGSS of 100pa, and, unlike the 2n4117a, it does list its Id(off) current leakage of 50pa.

`` Any other ideas?``

• Hi @NeverDie,

I also have the strong feeling that a couple of voltage detectors could make it much easier, yet β due to picoamps leakage β more effective.

Such, in the couple of last days I've tried to reproduce the UB40M circuit with real transistors. Perhaps, when you build a die you can construct every transistor with the parameters you need, but I admit it was not a trivial task to pick anything suitable from a catalogue. I defined no strict constraints to the application, rather tried to be opportunistic and use whatever works. There were some assumptions though:

• Input voltage is defined by the solar cell and is somewhere between 2V and 3V. In the deign below it's set to 2.5V.
• The short circuit current for the cell should not extend 50 nA. I've limited it down to 25 nA with the Rcell = 2.5V/25nA = 100MΞ©.
• The harvester should be able to charge 22Β΅F storage capacitor - this capacity should be enough to send a single non-connectable BLE advertisement.

I haven't bothered to find the low leaking MOSFETs and chose something small, handy to solder, cheap, and in stock. That turns out to be power MOSFETs in PowerPAK SC-70 package from Vishay. The nomenclature is SiAxxxDJ where the xxx is what you may see in the circuitry below. For example, 421 stands for SiA421DJ.

The core of the circuit is the pretty much of the UB40M reference design. The series of MP5-MP7/MN6-MN8 triggers will pull Reset line high when VREF will become low. This will happen when MN5 will pull it down, and depends on the Vdet voltage. At the same time, the MP4 will be turned off by VoutL (Reset) thus preventing VinL from being unintentionally pulled to the GND. The MP3 is used as a diode there.

I failed to create the VREF voltage in the way it was defined in the Bristol paper. With the circuit powered by the very low-power source, it suffers from transient processes a lot. To address that, I went for more complicated solution with couple of triggers controlled by Rdet1+Rdet2 divider. The divider also allows to tune the circuit to better match source and storage capacitor.

Finally, there is a 1k load attached to the Vin line. It discharges the Cstore capacitor as soon as the Reset will be set high. Upon discharge, the voltage detector will went reset the Vdet and the Cstore will be charged back.

In my KiCad ngspice it looks as follows. With Vcell=2.5V, Icell=25nA the Vin oscillates between 1.4V and 1.95V. Although this is way below required 1.8V for most of sensors and MCU, raising solar cell voltage to 3.5V will shift the voltages to the usable range.

Discharge current is limited solely by the Rload=1k. At the same time, average current consumption of the harvester is about 3nA - the blue line I(Rharv). Solar cell load is below 10 nA - the yellow line I(Rcell). However, due to non-linear nature it's hard to predict how the line will look like with a real cell. Probably, it's better to simulate it with a current source, I don't know. The red line Vdet shows how the voltage detector works.

To be honest, I'm quite unhappy about the circuit.

First of all, it uses a lot of transistors, please compare this to the BJT harvesters you're working on. Also, many of them work on subthreshold voltages, and this makes it relatively hard to to tune. But worse, real devices will likely to suffer from the voltage interference which makes the whole circuit too fragile. Taking in account the money to build it (even with \$0.40 per FET), it turns out the circuit shall be considered rather impractical.

• You may be unhappy with your circuit at the moment, but to my eyes it looks like you've got some traction and you've made a good start.

I haven't bothered to find the low leaking MOSFETs and chose something small, handy to solder, cheap, and in stock. That turns out to be power MOSFETs in PowerPAK SC-70 package from Vishay. The nomenclature is SiAxxxDJ where the xxx is what you may see in the circuitry below. For example, 421 stands for SiA421DJ.

Not sure if what I'm finding out about my Vishay SiRA80DP mosfet might be similar to your Vishay mosfet, but I'll mention it anyway as a possible "heads up": I'm finding evidence of a pretty wide discrepancy between Vishay's SPICE model and what's physically true by measurement. Although I don't yet have a picoammeter (I'll be building one soon) for a more definitive test, I was able to do a relevant measurement with the voltage follower I built (see picture in previous post). The test circuit, to indirectly compare leakage of two different mosfets, was this:

If the mosfets were ideal and there were no leakage in either mosfet, then presumably the voltage measured at VF1 and VF2 would both be 3.3v. But, of course, they're not ideal: simulation shows that VF1 would be 3.12v an VF2 would be 1.59mv. I built the circuit and the actual measurements, taken with my voltage follower and a DMM, were almost the complete opposite: VF1=280mv and VF2=3.01v. i.e. the Vishay mosfet measured as far more leaky than predicted by TINA TI spice simulation of Vishay's SPICE model, and the other N-Channel mosfet (one of two mosfets on Diodes Incorporated DMC2700UDM-7) measured as far less leaky than predicted. It's a very easy test to perform... ahem, that is, if you are in possession of a 10 gigaohm resistor and a buffer (voltage follower) with a picoamp input bias.

Edit1: Come to think of it, a better way to test would be to use no resistor and just measure how much leakage there is with the gate set to GND. The leakage would likely be in the nanoamps, so it could be measured with a uCurrent Gold, or equivalent, which maybe you already have in your possession. Setting the DS voltage to whatever is listed in the datasheet for the leakage value would then give a number that can be directly compared to the leakage entries in the datasheet. Much easier and doesn't require high value resistors or exotic buffers! Obvious in retrospect. May or may not require a picoammeter, depending on the mosfet. To cover all the cases, I'll try these measurements after I build my picoammeter (soon!). I'll be building the inexpensive picoammeter designed and already vetted by an EEVBlog user named "Gyro":

https://www.eevblog.com/forum/beginners/static-control-requirements-for-picoamp-measurements-using-ucurrent-gold/msg3068708/#msg3068708
For anyone interested, you can find photos and all the details here: https://www.eevblog.com/forum/projects/picoammeter-design/msg790045/#msg790045
Rather than reduced to a nice simple PCB, the critical parts are air-wired, which is deemed the superior method according to the op-amp's datasheet. In addition, to better ensure accuracy, the DUT and all the measurement instruments should be enclosed together within conductive shielding as a countermeasure against external interference when measurements are taken.

• I tried soldering wires directly to some femtofet's, but I've concluded they either need to be locked down to a larger substrate with glue or else properly reflowed in an oven. Otherwise, they behave like super energetic tiddly-winks: even the slightest bump when attaching the first wire will make the femtofet jump great distances, most likely never to be found or seen again. I lost 3 in a row that way, so my next attempt will use glue and very fine wire. I have an idea on how I might pre-align the wires prior to soldering, which is probably necessary in order to hand solder such a tiny thing.

My first attempt at a picoammeter is almost built. Unfortunately, it might might work well only with a DMM and not so well with an o-scope. So, I may have to build something different for that.

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