Here is a fiber laser machine example: https://mylasermart.com/product/ultra-high-speed-laser-machine/
It uses 50W fiber laser. Minimal track width is 0.05 mm! Space between tracks is 0.025 mm which is limited by the beam size. Precision ±2 µm.
This particular one doesn't look any cheap, but it gives the strong hint what to look for.
@NeverDie Yeah, it's a very interesting option! Similar approach might be to use a UV printer. The UV paint is known to be resistant to FeCl3 and hence results in nice and clean edges. But that's subject of paint and a laser engraver could be used over UV paint too.
On the other hand, a fiber laser might be a nice all-in-one solution. It can do the PCB routing, can cut the board edges, and drill everything in one pass. After that, the same device can be used to manufacture solder mask using a kapton tape and also engrave the silk layer on top of it. Finally, it can cut stencils.
The only missing part is the through hole plating. I still have concern that laser drilled the edges will be good enough for metalization, this has to be checked. But a previously drilled and plated board is much easier to etch with laser rather than a milling machine.
@NeverDie Yeah, this is awesome hack! I'll followup in the CNC thread :+1:
Regarding the PCB milling, I found myself thinking fairly often about full-cycle manufacturing too :-)
I usually do small boards, up to 4x4 inch. For this size it should be possible to build an affordable, but highly capable machine. Some thoughts on it:
High precision. The machine must be able to cut tracks and pads as thin as 6 mils (0.15 mm), but 5 mils would be really nice to achieve. Because of this I'm more inclined to laser cutting. On a milling machine 6 mil gaps between tracks will be hard to do. Another advantage of laser cutting is that it won't tear tiny tracks off the board. Perhaps, even a copper foil can be laser cut. But there's also a spoon of tar: the copper is known to be very reflective and imposes higher requirements to the laser cutter - the price may increase. Another thing to note is that the laser may be not so good at removing large surface areas.
Kapton tape for solder mask. For sticky mask to apply, I'm also thinking about some kind of a pallet - this would allow to use cheap polyimide tapes from eBay. Alternatively, non-sticky masks can be laminated. Laminated masks will stick stronger and can be two sided - think of it as about three and more layers. Again, laser cutting is preferred here.
Engraving of the silk layer. Laser could be also used for high-res silk layer over the kapton tape. With laser used, the difference in distances from the head to surface because of the copper layer is not an issue. Engraving on both copper and substrate is also possible.
Interchangeable heads? Probably, no. The cost of the working head, either laser or milling, will likely dominate over the cost of other components - the machine is small. Seems it's more reasonable to have different machines.
Assembly machine. This would be my favorite, but first things first.
Hi @NeverDie,
The 39% is a HUGE!
I think there is must some fundamental limit on how much we can get from these oscillations of the, well, Ether. Or is it the quantum vacuum? Or the strings? Well, the very last name to this kind of shit is the time crystals. And, no matter what the name is, the shit can oscillate, and these oscillations are the essence of the energy. So, while currently most of electronic devices employ electrons as drivers, I'm wondering would it be possible to build an electron-less system where the oscillations (aka waves) may be passed through a number of transformations, and this will bring us to some useful things.
Actually, there is RF and optics which works exactly like that. There is also a number of RF harvesters to collect the energy, but the energy is used mostly to push electrons forward, i.e. produce direct current. That's understandable - most of devices are DC. But creating some kind of a microwave transistor would be just rad.
Gah! I've lost the ball :disappointed:
No progress on discrete harvester, sorry. Also, the PV panels I got earlier were shelved until better times.
I still monitor a couple of the SPV1050 devices though. They're running from various PV panels that I switch from time to time. The load is an nRF52833 beacon and sometimes an IMU broadcasting every one second at 0dBm to 8dBm and reporting voltage of attached ML2032 battery to my phone.
My experience is that a tiny PV panel cannot sustain the device working online. By online I mean that both the device and the harvester power consumption exceeds the panel capabilities, so the battery slowly decays. A bigger panel can address the issue. I still unsure how much we will win if a more efficient online harvester like AEM10941 or even more efficient R1800K will be used. A batch harvester is definitely the way to go.
But how about you? Have you had a chance to build anything yet?
@NeverDie Yeah, soldering those tiny packages is sort of PITA. For experimenting with them I thought on a breadboard friendly PCB with the package footprint.
Hi @NeverDie,
I also have the strong feeling that a couple of voltage detectors could make it much easier, yet – due to picoamps leakage – more effective.
Such, in the couple of last days I've tried to reproduce the UB40M circuit with real transistors. Perhaps, when you build a die you can construct every transistor with the parameters you need, but I admit it was not a trivial task to pick anything suitable from a catalogue. I defined no strict constraints to the application, rather tried to be opportunistic and use whatever works. There were some assumptions though:
I haven't bothered to find the low leaking MOSFETs and chose something small, handy to solder, cheap, and in stock. That turns out to be power MOSFETs in PowerPAK SC-70 package from Vishay. The nomenclature is SiAxxxDJ where the xxx is what you may see in the circuitry below. For example, 421 stands for SiA421DJ.
The core of the circuit is the pretty much of the UB40M reference design. The series of MP5-MP7/MN6-MN8 triggers will pull Reset line high when VREF will become low. This will happen when MN5 will pull it down, and depends on the Vdet voltage. At the same time, the MP4 will be turned off by VoutL (Reset) thus preventing VinL from being unintentionally pulled to the GND. The MP3 is used as a diode there.
I failed to create the VREF voltage in the way it was defined in the Bristol paper. With the circuit powered by the very low-power source, it suffers from transient processes a lot. To address that, I went for more complicated solution with couple of triggers controlled by Rdet1+Rdet2 divider. The divider also allows to tune the circuit to better match source and storage capacitor.
Finally, there is a 1k load attached to the Vin line. It discharges the Cstore capacitor as soon as the Reset will be set high. Upon discharge, the voltage detector will went reset the Vdet and the Cstore will be charged back.
In my KiCad ngspice it looks as follows. With Vcell=2.5V, Icell=25nA the Vin oscillates between 1.4V and 1.95V. Although this is way below required 1.8V for most of sensors and MCU, raising solar cell voltage to 3.5V will shift the voltages to the usable range.
Discharge current is limited solely by the Rload=1k. At the same time, average current consumption of the harvester is about 3nA - the blue line I(Rharv). Solar cell load is below 10 nA - the yellow line I(Rcell). However, due to non-linear nature it's hard to predict how the line will look like with a real cell. Probably, it's better to simulate it with a current source, I don't know. The red line Vdet shows how the voltage detector works.
To be honest, I'm quite unhappy about the circuit.
First of all, it uses a lot of transistors, please compare this to the BJT harvesters you're working on. Also, many of them work on subthreshold voltages, and this makes it relatively hard to to tune. But worse, real devices will likely to suffer from the voltage interference which makes the whole circuit too fragile. Taking in account the money to build it (even with $0.40 per FET), it turns out the circuit shall be considered rather impractical.
:man-shrugging:
@NeverDie said in 💬 The Harvester: ultimate power supply for the Raybeacon DK:
Glad you asked, but it turns out not to be happy news. As it stands, it's a very constant 28.73ua leakage, which is obviously pretty terrible.
The circuit has so low leakage mostly due to the gigohmic resistors. In particular, those 300 pA bumps on AM3 may be due to the R4 limits (3V / 10 gOhm). And it looks like the right thing to do for a BJT. Oppositely, MOSFETs can be used as ultra strong resistors themselves. I.e. should you put several in series and the leakage drops.
I.e. it might be reasonable to drop a MOSFET in the place of T5+T6, and yet another gigohm resistor will cut the T4 leakage down.
@NeverDie said in 💬 The Harvester: ultimate power supply for the Raybeacon DK:
Maybe this kind of separation better answers your question about the leakage?
Definitely. Thanks a lot!
It would also be interesting to know measurement from the AM4 when the LED driver circuit is off. You see, MOSFETs are mainly characterized by the subthreshold leakage current between D and S - the AM4 has it.
@NeverDie Congratulations! Looks very holistic. The only model needed is 2SD2704 - cool! :the_horns:
I'm unsure though will it be possible to substitute the star from three 100 pF capacitors with a single one 68pF?
Could you also isolate T4 and T5 from the oscillator, please, so the AM1 won't measure their leakage? It's interesting to compare that cascade to a MOSFET.
@NeverDie said in 💬 The Harvester: ultimate power supply for the Raybeacon DK:
Unless you can think of a way to somehow roll-your-own ultra low power supervisor, I'm not aware of anything else. I suspect that maybe the Michigan team that built the Cortex M0 with the ultra tiny solar cell could easily beat both the ABLIC and Vishay supervisors--I'm still gobsmacked by what the Michigan team accomplished-- but at the moment I don't understand how to do the kind of leakage supression that's the foundation of what the Michigan team did. On my one and only attempt, after toying around with it, I was able to get one simulation that seemed to oscillate under very narrow conditions without meaningful leakage, and at first that gave me some hope. However, at the time I didn't see a way to extend that tiny, somewhat dubuious success toward anything useful. Having read the Michigan paper, can you get a leakage supression simulation working, either from their schematic or from one of the other papers? If so, that would be enormously helpful. I could post the simulation that I tried if you wanted to take a stab at it. It's not much, but pretty much anything, even an unremarkable crippled anything, is more than what typically gets published in the academic papers.
IMHO this is the promising direction to go. I haven't analyzed the circuits yet, but the super cut-off idea is dead simple - instead of grounding transistor gates, they have to be under-driven with a negative voltage. This should effectively remove free electrons from the depletion region and hence minimize drain–source leakage. Unfortunately, this requires to maintain an additional negative power source which may draw it's own current to operate. The overhead may be to expensive for a circuit with few gates, but seems well worth it for a processor core with thousands of transistors. What's good, is that this technique clearly separates optimization from the logic. In SPICE it might be easily simulated with a second voltage source, for example, at -0.1V. BTW, for the same reason the higher Vth - the lower DS leakage should be expected.
I'm thinking about building the UB40M alike circuit with any transistors. Well, the FemtoFET series is very small indeed. But size of the biggest package codename F5 is 0.73x1.49 mm which is roughly the same size as 0603 components. With proper PCB footprint soldering them should not be an issue. All in all, what must we expect from a modern high performing transistor?
Unfortunately, my ngspice doesn't work well with the Level 7 model the TI provides. So to have anything tangible to play with I've noticed a complimentary pair from Vishay, Vth=2.5V, Vds=150V: SiA485DJ (P-channel) and SiA446DJ (N-channel). PowerPak SC-70 package also looks appealing - 2x2 mm will help save PCB space, but still not microscopic.
Unfortunately, the P-MOS has no SPICE model, damn it. I'll try to replace it with Si1411DH which parameters looks very close to the SiA485DJ, and there are SPICE models for it.
Some leakage curves for the FETs in the 0...5V range:
Interesting, that the faster raises the voltage - the more leakage occurs. For example, the same chart for 1s raise:
@NeverDie Cool! :+1:
A supervisory circuit will be needed between the store and the load anyway. BTW, most of ultra-low power supervisors will consume tens of nanoamps. Does it mean it has to be a low leaking FET? :-)
@NeverDie said in 💬 The Harvester: ultimate power supply for the Raybeacon DK:
a couple of interesting things about the NPN ring oscillator are worth mentioning:
It works over a wide voltage range: from 300mv up to 20v.
In contrast to the NFET ring oscillator, where when an NFET is "OFF", it continues to leak current, in the NPN ring oscillator, when the NPN is "OFF", it leaks almost no current at all--maybe just a couple picoamps or less.
Yeah, it is impressive, no doubt. I'm not confident with so low-power circuits and were taught that MOSFETs are leaking less, and BJTs are requiring more current to drive. But this discussion disregards it all, at least when it comes to discretes :-D
@NeverDie Regarding components selection - unfortunately, that's true, too few manufacturers provide that data in a table to compare and select from. So far we have the FemtoFET series from Texas, the FETs listed in the Nexperia's AN90009 paper, and the ALD FETs. General recommendations for a low-lakage FET may be:
However, an attempt to select low-leakage FETs using these recommendations will certainly fail. It rather seem more depends on specs a manufacturer tries to warrant. For example, in theory high drain-source voltage may imply lower leakage at low voltages. But usually lower power transistors are leaking less.
Such, all Vishay specs I've read for more or less matching transistors mention exactly the same values for GS and DS leakage. Similarly, all ALD transistors have very low leakage because the ALD is working hard to manufacture them so. But I admit, for unknown reason any of those low-leakage FETs are ridiculously small, it's very rare when any dimension is bigger than 1mm.
Looks like if we really want it low, we must accept the size. On the other hand, some youtubers do solder even 008004 which are way smaller.
Alternative way is to choose a couple of transistors and measure them. I think that 1µA leakage from datasheet will barely go over 10nA in practice, so your choice should be just fine.
BTW, SPICE models usually operate with physical dimension, so should be accurate enough when it comes to comparing leakage of different items.
@NeverDie In SPICE the ring oscillator works just fine. I don't see why it may be hard to have it oscillating with any FET. However, due to the fact it's perfectly balanced (at least in it's current form) across all the three transistors it may be somewhat reluctant to start.
Here is how I get it in the light of the power consumption. For convenience, I've re-enumerated all components left to right.
Phase 1. I'm not going to cover the circuit boot and will start at the moment when the Q3 is closed. In the closed state VF3=0 it will tie the Q1 gate and the bottom pole of C1 to the ground. The Q1 is closed, and the C1 will be charging via R1 resistor. The R1 will set the charge time for C1.
At the same time, due to the closed Q3 the voltage source will be grounded via R3 and this results in extra leakage Vin/R3. At this phase, the overall current consumption will be about I ≈ Vin/R2 + Vin/R3
Phase 2. The phase 1 will last until C1 will be charged to the Q2 gate threshold voltage. After that, the Q2 which was previously open due to the C1 voltage drop, closes, and this will tie VF2 to the ground and open the Q3.
The opened Q3 will shift ground level for the C1 thus doubling the VF1 voltage. The C1 will start discharging down to zero until VF1 won't balance VF3. Actually, the C1 it will be charged from the opposite side via R3. The R3 defines period of the stage 2. Consumption current should be about the same I ≈ Vin/R2 + Vin/R3. Please note, since the Q2 is not participating in C1 charge/discharge it should be safe to keep R2 resistance much higher than R1 and R2, like 300g or so, and decrease the circuit consumption.
However, it seems slightly more complicated than that. Due to FETs non-linearity, at marginal gate voltages there is some drain–source resistance. Despite the Q1 is open with VF3 voltage, it's not enough to have the C1 grounded, and this is why the circuit works at all. Instead, both C1 and the voltage source will be leaking via the Q1. While voltage source is limited by R2, the leakage for C1 may be quite high and require extra attention. Luckily, this is not true for the SiSA40DN - the C1 slowly discharges via Q1 and this compensates for leakage from the voltage source via R1.
Repeat. Upon C1 discharge it's going to close Q2 and raise gate voltage on Q3. The Q3 opens, VF3 voltage drops, then Q1 closes too, and the C1 starts charging back again.
Well, as for an astable oscillator the circuit looks cool, definitely would be interesting to build. But for energy harvesting purposes I'd prefer some UB40M variation - IMHO it's much cleaner from the point of parasitic leakages. Especially if taking in account those leakage optimization techniques like we've seen for the super cutoff gates.
So, while here I've decided to close my TODO list. The revision 1.4 is likely to be the last chapter in this design, and now it can be considered safe to order. It introduces some important final touches to the board, in particular:
The orientation key (diameter 2.1mm) on the board edge. It's located between the Tag-Connect and the board main area, and initially can be used as an eyelet. After the Tag-Connect removal it works as an orientation key for the board.
Full rework of the silk layer. Just to mention few: I hid all designators and decorated the board with eye catchy "52" over the nRF52 MCU, touched the antenna outline, and moved the git hash to the mainland.
Review and cleanup the ground plane. The changes were tiny so it shouldn't detune the antenna, but aesthetics were definitely improved. You may also want to order the board in Afterdark colors now:
Have fun!
The revision 1.3 is here! It adds hardware RESET feature to the SW2 push button, as well as to the SWD port. Not a big deal when attached to debugger, but so handy on the go.
Please note, the change make break your firmware because SW2 was mapped to P1.02 GPIO and now linked to the P0.18 / RESET.
@NeverDie The circuit looks like a parametric oscillator indeed, and it is cool! What I like about it (of course, if I get it right) is that it employs only one transistor model, and those gigohm resistors are maintaining the current consumption really low. For this reason there is no need to carefully select the transistors - everything that has appropriate gate threshold value should work just fine.
On the other hand, it might happen that if you need it to work at higher frequency you will have to lower resistance of the R1-R3 and thus increase the current consumption.
BTW, accordingly to datasheet those particular FETs has quite high D-S leakage up to 1 µA. But again, should not be an issue. Perhaps, while you're here and have tools to measure picoamps, you might be interested to grab a couple of those Femto N-FETs or other officially low leakage transistors, just to compare them to others. In particular, put them against a usual FET in the super-cutoff state, i.e. when supplying negative gate-source voltage.
And, of course, I wish you best of luck with this experiment :biohazard_sign: and look forward for your updates! :hand_with_index_and_middle_fingers_crossed:
@NeverDie More than enough :-)
It seems there are two more or less working BJT based circuits which can be tested easily - the 3 nA oscillator which you've modeled with different transistors, and the solar motor project. Both are way more low-power than existing harvesters.
The FET based circuit remains in doubt until suitable components were selected. But IMHO putting some FETs to test to measure D-S leakage would surprise with numbers.
Regarding application, I have no requirement for so ultra-low power system, but many examples do measure something and then broadcast the data via BLE. They may even use harvesting switches, like the On Semi BLE-SWITCH001-GEVB evaluation kit. Maybe we can also consider something like this? If you have any good app on your mind lets aim at it.