@marceloaqno: ok so here are my conclusions:
After going through the schematics of the OPi Plus2e I realized that the H3 has dedicated pins for NAND/eMMC, which is probably not the case for the H2+ in the OPi zero. They used the pins of SPI1 for a status LED and a "MUTE" net, which is not connected anywhere so at first I was like "wtf?"...
So, the SPI0 is free for usage out of the box and the .fex does not need to be modified. Summed up:
If the OPi to be used has "SPI0" in the GPIO header, no .fex modifications are necessary. CE and CN/CS/CSN pin can be chosen freely (?), I picked it like this:
ce - gray - pa13 - PHYSICAL pin8 - LOGICAL pin13 (1-1)*32 + 13
cn - blue - pa14 - PHYSICAL pin10 - LOGICAL pin14 (1-1)*32 + 14
If another pin is chosen, the pin number can be calculated with that formula: (position of letter in alphabet - 1) * 32 + pin number (from: https://linux-sunxi.org/GPIO)
The pinout of the connector can be found here: https://linux-sunxi.org/Xunlong_Orange_Pi_Plus_2E#Expansion_Port (SPI0 pins are PC0-PC2 or 19,21,23)
After connecting the physical pins 8,10,19,21 and 23 to the nrf24 (and pin 1 for 3.3v), following command was sufficient to set up mysgw and get the nrf24 to respond:
./configure --spi-spidev-device=/dev/spidev0.0 --my-transport=nrf24 --my-rf24-ce-pin=13 --my-rf24-cs-pin=14