Arduino D10 initialized with NRF, even when not used (Version 2.0.0 stable)



  • Hi,

    Following setup:
    ATmega328P with NRF24L01+ and MySensors 2.0.0 sketch on it,
    NRF connected to hardware SPI, CE on D5 instead of D9 (Arduino numbering) and CS on D6 instead of D10.

    Everything is set correctly in the sketch, but still D10 will be initialized and put high, although not used.
    The right CS pin will be used later, but this initialization of D10 is just wrong.

    If I enable SoftSPI and set the D11-D13 as the ports to be used (so, using same ports but bit banging instead of HW), everything works correctly.

    Had a quick check in the sources, but could not find where D10 is initialized.
    This effect vanishes, if I change the default setting in the MyConfig.h

    Tested with Arduino 1.6.9 and 1.7.10.


  • Admin


  • Admin

    This is an issue with the HW SPI port in the atmega328. If configured as an input, the master spi port will turn into a slave, if SS pin is low.

    Atmega328p datasheet, section 19.3.2:

    When the SPI is configured as a Master (MSTR in SPCR is set), the user can determine the direction of the SS

    pin.

    If SS is configured as an output, the pin is a general output pin which does not affect the SPI system. Typically, the pin will be driving the SS pin of the SPI Slave.

    If SS is configured as an input, it must be held high to ensure Master SPI operation. If the SS pin is driven low by peripheral circuitry when the SPI is configured as a Master with the SS pin defined as an input, the SPI system interprets this as another master selecting the SPI as a slave and starting to send data to it. To avoid bus contention, the SPI system takes the following actions:

    1. The MSTR bit in SPCR is cleared and the SPI system becomes a Slave. As a result of the SPI becoming a Slave, the MOSI and SCK pins become inputs.

    2. The SPIF Flag in SPSR is set, and if the SPI interrupt is enabled, and the I-bit in SREG is set, the interrupt routine will be executed.

    Thus, when interrupt-driven SPI transmission is used in Master mode, and there exists a possibility that SS is driven low, the interrupt should always check that the MSTR bit is still set. If the MSTR bit has been cleared by a slave select, it must be set by the user to re-enable SPI Master mode.


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